Embedded Package Thickness Reduction via Stacked Chip Nesting
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Solution Overview
Problem
The increasing number of vertically arranged chips in embedded packages leads to a rise in the number of circuit layers, resulting in an increase in package thickness, which hinders miniaturization efforts in portable electronics.
Innovation Solution
The implementation of a stacked embedded package design where first and second semiconductor chips with sunken areas are arranged facing each other, surrounded by a core layer with circuit patterns, and connected via bumps and vias to reduce thickness and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of vertically arranged chips is increased to achieve high capacity and miniaturization, then the mounting efficiency is improved, but the thickness of the embedded package increases due to the proportional increase in circuit pattern layers
Solution Approach 1:
The patent transitions from a conventional planar arrangement of chips to a three-dimensional stacked configuration where chips are vertically arranged and embedded within the substrate. This dimensional change allows multiple chips to occupy the same footprint area, dramatically improving mounting efficiency while the embedding technique prevents proportional thickness increase by integrating chips into the substrate depth rather than stacking layers horizontally
2Area of stationary object
If multiple chips are vertically arranged to reduce package area, then the package footprint is reduced, but the number of circuit layers increases proportionally leading to increased thickness
Solution Approach 1:
The patent embeds multiple semiconductor chips within the substrate in a nested configuration, where chips are positioned at different depths and surrounded by the substrate material. This nesting approach allows multiple chips to occupy a compact volume without requiring proportional increases in any single dimension, thereby reducing package footprint while controlling thickness through vertical integration
3Volume of moving object
If chips are embedded in the substrate to achieve miniaturization, then the package size is reduced, but the complexity of electrical connections between chips and external terminals increases
Solution Approach 1:
The patent introduces a core layer as an intermediary structure that contains circuit patterns and via holes to facilitate electrical connections between embedded chips and external terminals. This core layer acts as a mediator that simplifies the complex routing required for multi-chip interconnections by providing a structured pathway through the substrate, thereby reducing connection complexity while maintaining miniaturization benefits
Data Source
AI summary
An embedded package includes a first semiconductor chip having a first conductive line which has a first sunken area, a second semiconductor chip having a second conductive line which has a second sunken area, wherein the first semiconductor chip and the second semiconductor chip are arranged facing each other, and wherein the first sunken area and the second sunken area are arranged facing each other, a core layer surrounding the first semiconductor chip and the second semiconductor chip, wherein the core layer has a first circuit pattern coupled to an external terminal; and a bump formed in the first and second sunken areas, wherein the bump is coupled to the first circuit pattern.