Embedded Package Structure With Stacked Chips And Vertical Interconnects
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Solution Overview
Problem
Conventional embedded package structures face issues such as parasitic effects and signal degradation due to numerous metal routing layers, leading to larger sizes and reduced compactness, which complicates design and affects performance.
Innovation Solution
An embedded package structure comprising a metal substrate with stacked chips electrically connected through a patterned metal layer and insulation material, featuring a simplified redistribution layer design with vias for efficient interconnection, using materials like copper or Cu alloys, and including passivation layers for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous metal routing layers are used to connect chips, then electrical connection between chips is achieved, but parasitic effects increase and signal quality deteriorates
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical interconnection through stacked chips and vias. Multiple chips are stacked vertically with electrical connections established through vias penetrating insulating layers, converting horizontal signal routing into vertical pathways. This dimensional change reduces the number of metal routing layers needed while maintaining connection functionality.
Solution Approach 2:
The patent implements nested structure where multiple chips are stacked vertically within a compact package. Each chip is positioned at different vertical levels, with lower chips nested beneath upper chips. Electrical connections are established by routing signals through vias that penetrate through multiple insulating layers to reach corresponding pads on different chip levels, creating a nested three-dimensional interconnection architecture.
2Reliability
If numerous metal routing layers are used to connect chips, then electrical connection is achieved, but signal transmission distance increases causing intensity deterioration
Solution Approach 1:
The patent employs vertical stacking to reduce horizontal signal transmission distance. By positioning chips at different vertical levels and establishing direct vertical connections through vias, the signal path is shortened from extensive horizontal routing across multiple metal layers to compact vertical pathways, thereby reducing transmission distance and signal attenuation.
Solution Approach 2:
The patent extracts and eliminates unnecessary metal routing layers from the conventional planar architecture. By transitioning to vertical interconnection through vias and stacked chips, the design removes redundant horizontal routing paths, keeping only the essential connection pathways needed for electrical interconnection, thus reducing overall signal transmission distance.
3Adaptability or versatility
If lots of chips are placed inside the package, then functionality is enhanced, but package size increases
Solution Approach 1:
The patent utilizes three-dimensional vertical stacking to accommodate multiple chips within a compact footprint. Instead of placing chips side-by-side in a planar arrangement that increases package area, the design stacks chips vertically at different height levels, connecting them through vias. This transforms the package architecture from two-dimensional expansion to three-dimensional utilization, enhancing functionality while maintaining compact size.
Solution Approach 2:
The patent implements nested stacking where multiple chips are positioned vertically within the same horizontal footprint. Lower chips are nested beneath upper chips, with all chips occupying approximately the same planar area but distributed across different vertical levels. This nested arrangement allows multiple functional chips to be integrated without increasing the overall package footprint.
Data Source
AI summary
The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.