Embedded Package Trench Design for Bump Exposure
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Solution Overview
Problem
Existing semiconductor package technologies face challenges in minimizing size and efficiently exposing bumps for interconnection, leading to misalignment issues during etching for via holes, which affects the drivability and size reduction of embedded packages.
Innovation Solution
An embedded package design where a chip is attached to a core layer with bumps on its surface, surrounded by a first insulation layer with strategically formed trenches to expose the bumps, allowing for reduced interconnection line length and improved accessibility, and a method of fabricating this package involving the formation of trenches in the insulation layer to expose the bumps simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip is embedded in the package substrate to minimize package size, then the package size is reduced, but the bumps become difficult to access for interconnection
Solution Approach 1:
The patent divides the insulation layer into multiple sections by forming trenches that segment the embedded structure. This segmentation allows selective access to different bump groups while maintaining the embedded configuration, resolving the contradiction between compact packaging and interconnection accessibility.
Solution Approach 2:
The patent extracts specific portions of the insulation layer through trench formation to expose the bumps. By removing the insulation material in targeted areas, the bumps become accessible for interconnection while the rest of the embedded structure remains intact and compact.
2Manufacturing precision
If traditional etching methods are used to expose bumps, then individual bump exposure is possible, but misalignment issues occur affecting manufacturing precision
Solution Approach 1:
The patent combines multiple bump exposure operations into a single trench formation step. By forming one continuous trench structure that exposes multiple bumps simultaneously, the method eliminates alignment errors that would accumulate from multiple separate etching steps, thereby improving manufacturing precision.
Solution Approach 2:
The patent performs preliminary planning of the trench layout to ensure all required bumps are exposed in a single operation. The trench positions and dimensions are pre-determined based on the bump arrangement, allowing simultaneous exposure without subsequent alignment adjustments.
3Productivity
If the insulation layer completely covers the bumps, then insulation is provided, but interconnection efficiency is reduced due to longer interconnection lines
Solution Approach 1:
The patent applies local quality by providing insulation coverage only where needed and exposing bumps where interconnection is required. The trench structure creates local variations in insulation coverage, maintaining electrical isolation in most areas while enabling direct access to bumps for efficient interconnection in specific locations.
Data Source
AI summary
Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps.