Embedded Dielectric-Lined Package for Voltage Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging solutions, such as lead frame and metal clip based packages, have reached physical and performance limits in terms of power loss, current density, and efficiency, particularly due to soldered connections that impose practical limitations.
Innovation Solution
A semiconductor assembly with a package substrate featuring an interior laminate layer, metallization layers, and semiconductor dies embedded within, where dielectric material liners are used to enhance voltage breakdown resistance and electrical isolation, allowing for improved power handling and efficiency in a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional lead frame and metal clip based packaging solutions are used, then electrical interconnections can be established, but power loss increases and current density decreases due to soldered connections reaching physical limits
Solution Approach 1:
The patent extracts and eliminates the soldered connection element from the electrical interconnection path by using embedded semiconductor dies with direct metallization layer connections. This removes the weak link (solder joints) that limited current density and increased power loss, allowing direct bonding between package substrate metallization and semiconductor die terminals.
Solution Approach 2:
The patent employs composite material structures including laminate layers combining dielectric materials with embedded metallization, and uses dielectric liners with specific material properties to achieve both mechanical support and electrical isolation. The combination of different materials (metallization layers, dielectric liners, laminate substrates) creates a hybrid structure that overcomes the limitations of conventional single-material packaging solutions.
2Reliability
If semiconductor dies are embedded within laminate layer, then voltage breakdown resistance is enhanced, but device complexity increases due to multiple layers and materials
Solution Approach 1:
The patent implements nesting by embedding semiconductor dies within cavities formed in the laminate layer. The dielectric liner is nested on the semiconductor die surfaces, and the entire assembly is nested within the multi-layer package substrate structure. This nested arrangement provides voltage breakdown resistance while organizing complexity in a hierarchical manner.
Solution Approach 2:
The dielectric liner acts as an intermediary element between the semiconductor die and the surrounding laminate environment. It provides electrical isolation and mechanical support, mediating the interaction between high-voltage semiconductor components and the lower-voltage package substrate, thereby enhancing voltage breakdown resistance without requiring complete redesign of the entire package structure.
3Reliability
If dielectric liner is added on semiconductor die, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The dielectric liner is applied to the semiconductor die surfaces before embedding the die into the laminate layer. This preliminary action ensures that electrical isolation is established in advance, preventing potential breakdown paths before the die is surrounded by the laminate material. The liner is deposited on load terminals and edge regions that require isolation.
Solution Approach 2:
The dielectric liner is not applied uniformly across the entire semiconductor die surface, but rather selectively on specific regions requiring electrical isolation. The liner is deposited on load terminals, edge regions, and corners where voltage stress is highest, while leaving other areas exposed for electrical connection. This localized application provides necessary isolation while minimizing added manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced voltage breakdown characteristics, mitigates electromigration risks, and achieves high current density and efficiency while maintaining a small areal footprint, overcoming the limitations of conventional packaging solutions.
Implementation Method 1
a liner of dielectric material on the first semiconductor die, wherein the first semiconductor die is embedded within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die
Data Source
AI summary
A semiconductor package includes a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, a first semiconductor die that includes a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die that is opposite from the first surface of the first semiconductor die, and a liner of dielectric material on the first semiconductor die, wherein the first semiconductor die is embedded within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.