Embedded Packaging Preformed Vias Low Roughness Metal Posts

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Solution Overview

Problem

Current microelectronic assemblies face limitations in terms of compactness and efficient interconnection, which affects signal propagation speed and overall performance, particularly in high-speed operations.

Innovation Solution

The development of a microelectronic assembly featuring substantially rigid metal posts with low surface roughness, encapsulation, and an electrically conductive redistribution structure that connects terminals with metal posts, allowing for efficient electrical coupling and insulation, thereby enhancing interconnection density and assembly compactness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional packaging structures are used with higher surface roughness metal posts, then manufacturing is easier, but signal propagation time increases and interconnection efficiency decreases

Engineering Contradiction:
Improvesignal propagation speedVSAvoidmetal post surface roughness
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by controlling the surface roughness of metal posts to be less than 1 micron RMS, transforming the physical parameter of surface finish to achieve faster signal propagation and reduced signal loss, thereby resolving the contradiction between manufacturing ease and signal performance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses excessive action by implementing unusually low surface roughness requirements (less than 1 micron RMS) for metal posts, which exceeds conventional manufacturing standards, to achieve superior electrical performance and signal propagation characteristics

Inventive Principle:
Principle #16Partial or excessive action

2Volume of moving object

If interconnection density is increased to improve compactness, then assembly size is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveassembly sizeVSAvoidinterconnection structure complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the interconnection structure into distinct functional components: preformed vias in the substrate, separate metal posts with controlled roughness, encapsulation layers, and redistribution structures. This modular segmentation enables compact integration while managing manufacturing complexity through standardized processes for each component

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes another dimension by implementing three-dimensional packaging with metal posts extending vertically through the substrate thickness, creating vertical interconnections that reduce horizontal footprint and enable higher interconnection density without proportionally increasing manufacturing complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If metal posts with low surface roughness are used, then electrical connectivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidsurface roughness control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by pre-forming vias in the substrate before depositing metal posts, and by establishing surface preparation processes in advance that ensure the required less than 1 micron RMS roughness. This preliminary preparation of surfaces and structures enables subsequent manufacturing steps to achieve the desired electrical connectivity without requiring extreme precision throughout the entire manufacturing process

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10460958B2Method of manufacturing embedded packaging with preformed vias
Publication Date: 2019.10.29 ADEIA SEMICON TECH LLC
  • US10460958B2 patent drawing
  • US10460958B2 patent drawing
  • US10460958B2 patent drawing

AI summary

Microelectronic assemblies and methods of making the same are disclosed. In some embodiments, a microelectronic assembly includes a microelectronic element having edge surfaces bounding a front surface and contacts at the front surface; rigid metal posts disposed between at least one edge surface and a corresponding edge of the assembly, each metal post having a sidewall separating first and second end surfaces, the sidewalls have a root mean square (rms) surface roughness of less than about 1 micron; a encapsulation contacting at least the edge surfaces and the sidewalls; an insulation layer overlying the encapsulation; connection elements extending through the insulation layer, wherein at least some connection elements have cross sections smaller than those of the metal posts; a redistribution structure deposited on the insulation layer and electrically connecting first terminals with corresponding metal posts through the first connection elements, some metal posts electrically coupled with contacts of microelectronic element.