Embedded Metal Pad Bonding Structure for Void-Free Chip Stacking
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Solution Overview
Problem
In semiconductor device manufacturing, step differences at metal pads and adjacent bonding surfaces can lead to voids during bonding, resulting in yield drops and defects if not controlled within tolerance ranges.
Innovation Solution
The implementation of a semiconductor device structure with embedded metal pads and insulating layers, where barriers are strategically placed between the insulating layers and metal pads, and additional insulating layers are formed to fill gaps created during chemical mechanical polishing, ensuring planar surfaces and preventing voids at bonding interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polishing process is applied to planarize the bonding surface, then surface flatness is improved, but step differences at metal pads and adjacent bonding surfaces still occur causing voids
Solution Approach 1:
The patent applies preliminary action by performing an additional polishing process after forming the insulating layer to pre-planarize the surface before bonding. This preliminary planarization step ensures that the metal pad surfaces and adjacent bonding surfaces have matched heights, preventing step differences that would cause voids during bonding, thereby resolving the contradiction between achieving surface flatness and ensuring bonding quality.
2Reliability
If metal pads are embedded in insulating layers for bonding, then electrical connection is achieved, but step differences occur at metal pads and adjacent bonding surfaces
Solution Approach 1:
The patent applies local quality by forming an insulating layer that locally covers the metal pads and extends to the bonding surface. This insulating layer is specifically designed to have a thickness that matches the metal pad height, creating a locally planar surface around the metal pads. This local planarization ensures both electrical connection through the metal pads and surface planarity at the bonding interface, resolving the contradiction between these two requirements.
3Reliability
If step differences are not controlled within tolerance range, then voids occur during bonding, but additional processing steps increase manufacturing complexity
Solution Approach 1:
The patent merges the planarization function into the insulating layer formation process itself. By designing the insulating layer to have a thickness that automatically compensates for metal pad height variations, the patent combines the electrical insulation function with the surface planarization function in a single step. This eliminates the need for separate complex planarization processes while ensuring bonding integrity, thus resolving the contradiction between bonding reliability and manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bonding strength by eliminating voids and ensuring a firm connection between semiconductor chips, thereby improving yield and reliability.
Implementation Method 1
The top surfaces of the first insulating layer and the second insulating layer are bonded to provide a bonding interface
Implementation Method 2
a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer
Data Source
AI summary
A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.