Embedded Parity Coding with Tensor-Product ECC for Low-Latency Storage
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Solution Overview
Problem
Current channel encoding and decoding architectures, particularly those using low-density parity check codes, face challenges in efficiently encoding and decoding data streams due to high latency, data rate, and memory size issues, especially when dealing with large block sizes and noisy channels.
Innovation Solution
The implementation of a tensor-product code (TPC) encoder and decoder system that uses a parity generation module, interleave module, and LDPC parity bit generator to generate and concatenate parity bits with user data, employing a generator matrix and circulant matrices to optimize encoding and decoding processes, while also incorporating Reed-Solomon parity bits for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-density parity check codes are used for error correction, then reliability is improved, but latency and memory requirements increase
Solution Approach 1:
The patent segments the LDPC encoding process into multiple parallel stages, where different portions of the codeword are generated simultaneously using separate processing units. This parallel segmentation reduces the overall encoding latency while maintaining the full error correction capability of the LDPC code.
Solution Approach 2:
The patent transforms the traditional sequential LDPC encoding approach into a multi-dimensional parallel processing architecture, adding temporal and spatial dimensions to the encoding process. Multiple encoding operations are performed concurrently across different processing elements, reducing latency without compromising reliability.
2Reliability
If low-density parity check codes are used for error correction, then reliability is improved, but memory size requirements increase
Solution Approach 1:
The patent extracts and removes redundant memory storage elements from the LDPC encoder architecture by optimizing the parity check matrix representation and utilizing systematic encoding structures. This reduction in memory size is achieved by taking out only the essential storage elements needed for maintaining error correction capability.
Solution Approach 2:
The patent changes the structural parameters of the LDPC code, specifically using quasi-cyclic LDPC codes with optimized block sizes and circulant matrix structures. These parameter changes enable more efficient memory utilization while preserving the code's error correction performance.
3Reliability
If tensor-product code with two levels of ECC is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the two levels of ECC (inner SPC code and outer LDPC code) into a unified tensor-product code structure with a single parity check matrix. This merging reduces device complexity by eliminating the need for separate encoding circuits for each level while maintaining the enhanced error protection capability of the concatenated code structure.
Solution Approach 2:
The patent designs a universal encoder architecture that can handle both the inner and outer code functions through a single multi-functional processing unit. This universal structure reduces complexity by making one device perform multiple encoding functions that would traditionally require separate dedicated circuits.
Data Source
AI summary
An encoder system includes a receive module that receives a data stream. A parity generation module generates parity bits based on the data stream and a tensor-product code. A parity insertion module combines the parity bits and the data stream to generate encoded bits.