Embedded Parity Coding with TPC-LDPC Decoding for Low-Latency Storage
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Solution Overview
Problem
Current channel encoding and decoding architectures, particularly those using low-density parity check codes, face challenges in efficiently encoding and decoding data streams due to high latency, data rate, and memory size issues, especially when dealing with large block sizes and error correction requirements near the Shannon limit.
Innovation Solution
The implementation of a tensor-product code (TPC) encoder and decoder system that utilizes a parity generation module, interleave module, and LDPC parity bit generator to generate and process parity bits, along with a decoder control module that manages truncation and puncture lengths to optimize code rate and sector length, while employing a soft-input iterative decoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used to achieve error correction near the Shannon limit, then reliability is improved, but latency and memory requirements increase
Solution Approach 1:
The patent divides the LDPC code into two levels: an inner level using simple parity check (SPC) codes and an outer level using LDPC codes. This segmentation allows the inner SPC layer to handle basic error correction with low latency, while the outer LDPC layer provides enhanced reliability. The staged approach reduces overall decoding latency compared to using full LDPC for all error correction needs.
Solution Approach 2:
The patent applies partial LDPC encoding by using SPC codes for the inner level error correction, which is sufficient for many practical scenarios. This partial application of the more complex LDPC technique reduces computational overhead and latency while maintaining adequate reliability for the specific application requirements.
2Reliability
If LDPC codes are used to achieve error correction near the Shannon limit, then reliability is improved, but memory size requirements increase
Solution Approach 1:
The patent segments the error correction functionality into inner SPC codes and outer LDPC codes. The inner SPC layer requires minimal memory for its simple parity check operations, while the outer LDPC layer uses optimized data structures (such as sparse representation of the parity check matrix) to reduce memory requirements. This segmentation significantly reduces overall memory usage compared to implementing full LDPC encoding for all error correction needs.
Solution Approach 2:
The patent applies different coding schemes to different parts of the data structure: simple parity check for inner-level symbols and LDPC for outer-level parity protection. This local differentiation optimizes memory usage by applying the more memory-intensive LDPC scheme only where necessary for achieving Shannon-limit performance, rather than uniformly across all data.
3Reliability
If tensor-product code with two levels of ECC is used, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the encoding and decoding processes into distinct inner and outer stages. The inner SPC encoding is computationally simple and can be implemented with basic XOR operations. The outer LDPC decoding, while more complex, benefits from the pre-processing by the inner layer, reducing the overall complexity burden. This segmentation allows each component to be optimized independently.
Solution Approach 2:
The inner SPC encoding performs preliminary error correction before the outer LDPC decoding stage. This preliminary action reduces the error burden on the outer LDPC decoder, allowing it to operate more efficiently with reduced complexity. The inner layer prepares the data in a form that is more amenable to the outer layer's processing requirements.
4Reliability
If larger block sizes are used for error correction, then reliability is improved, but processing time and memory requirements increase
Solution Approach 1:
The patent segments large data blocks into smaller inner-level symbols that are processed by simple SPC codes, with LDPC applied at the outer level. This segmentation enables parallel processing of multiple inner symbols simultaneously, maintaining high throughput while achieving the reliability benefits of large-block LDPC error correction through the outer layer.
Solution Approach 2:
The patent applies partial LDPC encoding to only the outer-level parity bits rather than to all data bits. This partial application reduces the computational overhead and processing time while still achieving the reliability benefits of LDPC codes, thereby maintaining higher data throughput.
Data Source
AI summary
A decoder system comprises a tensor-product code (TPC) decoder that decodes a received data stream to generate a decoded signal. A mark module that replaces low-density parity check (LDPC) parity bits of the decoded signal with 0s to generate a reset output signal. A deinterleave module deinterleaves error correction parity bits that are within the reset output signal to generate a deinterleaved signal that comprises a decoded portion and a concatenated portion. The concatenated portion comprises the error correction parity bits. A parity decoder module removes the concatenated portion from the deinterleaved signal.