Embedded Passive Devices in Power Delivery Network Substrates
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in miniaturization, power integrity, and interconnect efficiency due to increased power loop inductance, higher resistance in TSV interconnects, and disruptions between power and ground planes, which affect device performance and circuit reliability.
Innovation Solution
The implementation of semiconductor packages with embedded passive devices, such as decoupling capacitors, positioned in recessed areas between plated through hole vias, reduces pitch between vias, enhances capacitance density, and minimizes inductance loops, allowing for increased BGA IO density and improved power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If power and ground planes are configured far apart to reduce electromagnetic interference, then EMI is reduced, but power loop inductance increases
Solution Approach 1:
The patent embeds decoupling capacitors within recesses formed in the power plane, nesting the capacitor structures inside the plane itself. This allows the capacitors to be positioned close to the ground plane for low inductance while the overall power plane structure maintains EMI shielding distance.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional structure by forming recesses in the power plane and embedding capacitors within these recesses. This vertical dimensionality change allows compact placement while maintaining electrical performance.
2Reliability
If embedded passive devices are used to increase capacitance density, then power integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The power plane is segmented into multiple regions with recesses formed at specific locations where decoupling capacitors are needed. This segmentation allows targeted placement of embedded capacitors without requiring complete redesign of the entire power distribution network.
Solution Approach 2:
The recesses are formed in the power plane during the PCB manufacturing process before final capacitor placement. This preliminary action integrates the capacitor mounting structures into the base manufacturing flow, reducing the need for additional specialized processing steps.
3Productivity
If pitch between plated through hole vias is reduced to increase BGA IO density, then BGA IO density increases, but structural integrity of vias decreases
Solution Approach 1:
The power plane is designed with locally varied properties - dense via regions for high BGA IO density in non-critical areas, and reinforced regions with embedded capacitors where structural integrity is paramount. This local quality differentiation allows optimized via pitch in different zones of the PCB.
Solution Approach 2:
The patent combines multiple materials and structures - copper plating in vias, dielectric materials in recesses, and embedded passive devices - to create a composite construction that maintains via structural integrity while enabling reduced pitch arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables miniaturization of semiconductor packages, improves power integrity, and increases BGA IO density by reducing the footprint required for passive devices, thereby enhancing overall device performance and reliability.
Implementation Method 1
embedded passive devices, such as decoupling capacitors
Implementation Method 2
plated through hole vias
Data Source
AI summary
The present disclosure is directed generally to semiconductor packages, semiconductor package substrates, and methods for making them, which include packages substrates with embedded passive devices positioned between plated through hole vias configured for an improved power delivery network.