Embedded Passive Devices in Semiconductor Package Substrate
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Solution Overview
Problem
Conventional semiconductor package structures face challenges in miniaturization due to the large size of passive devices and high costs associated with horizontal terminal arrangements and redistribution layers.
Innovation Solution
The semiconductor package structure embeds passive devices with vertically arranged terminals within the substrate, utilizing conductive elements and wires to create a compact, cost-effective design by replacing traditional redistribution layers with vertical conductive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If passive devices are arranged horizontally with traditional redistribution layers, then electrical connectivity is achieved, but the package size and thickness increase
Solution Approach 1:
The patent transitions from horizontal arrangement of passive devices to vertical arrangement, changing the spatial dimension from 2D planar layout to 3D vertical stacking. Passive devices are positioned at different heights within the package, with conductive vias connecting terminals vertically through the substrate, thereby reducing the footprint area while maintaining electrical connectivity.
Solution Approach 2:
The patent embeds passive devices within the substrate volume rather than placing them on the surface. Multiple passive devices are nested at different depths and positions within the substrate, utilizing the three-dimensional space efficiently. This nesting approach allows multiple components to coexist in a compact volume without requiring extensive horizontal space.
2Reliability
If passive devices with large footprints are used, then electrical connectivity and functionality are achieved, but the package becomes larger and thicker
Solution Approach 1:
The patent arranges passive devices vertically at different heights within the substrate, with first terminals closer to the first surface and second terminals closer to the second surface. This vertical stacking in the Z-dimension reduces the horizontal footprint while maintaining proper electrical connectivity through conductive vias, thereby achieving compact packaging without compromising reliability.
Solution Approach 2:
Instead of extending passive devices horizontally to achieve connectivity, the patent inverts the approach by connecting terminals vertically through the substrate using conductive vias. The first terminal connects to the first surface and the second terminal connects to the second surface, reversing the traditional horizontal routing paradigm and reducing overall package dimensions.
3Ease of manufacture
If traditional horizontal terminal arrangements are used, then manufacturing is straightforward, but manufacturing costs increase due to redistribution layers
Solution Approach 1:
The patent eliminates the need for complex redistribution layers by arranging terminals vertically and connecting them through conductive vias. This vertical arrangement simplifies the manufacturing structure by removing redundant horizontal routing layers, reducing the number of fabrication steps while maintaining ease of manufacture through standard via formation processes.
Data Source
AI summary
A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.