Embedded Passive Semiconductor Layout for Higher Interconnect Bias
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Solution Overview
Problem
The integration of passive components in semiconductor substrates limits the applied bias due to the breakdown voltage of the passive components, necessitating alternative approaches for higher voltage applications.
Innovation Solution
A semiconductor structure is designed with a core layer containing a passive component, and a redistribution layer with multiple interconnects that include a first and second interconnect electrically isolated from the passive component, and a third interconnect connected to it, allowing for a significant difference in bias levels between these interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a passive component is embedded in the semiconductor substrate, then integration density is improved, but the maximum applicable bias is limited by the breakdown voltage of the passive component
Solution Approach 1:
The substrate is divided into multiple electrically isolated regions, each capable of accepting different bias levels. The first substrate region can accept a first bias while the second substrate region can accept a second bias that is higher than the first bias, allowing each region to be optimized independently for its specific voltage requirements.
Solution Approach 2:
Different regions of the substrate are assigned different electrical properties and bias levels according to their specific functional requirements. The first substrate region is configured with electrical characteristics suitable for lower bias operation, while the second substrate region is configured for higher bias operation, enabling each local area to operate at its optimal voltage level.
2Area of stationary object
If multiple components with different functions are integrated into a given area, then device size is reduced, but the bias application becomes more complex due to different breakdown voltages
Solution Approach 1:
The substrate is segmented into multiple electrically isolated regions that can be independently biased. This segmentation allows different bias levels to be applied to different regions without interfering with each other, simplifying the overall bias application strategy despite the presence of multiple components with different voltage requirements.
Solution Approach 2:
The patent introduces an additional dimension of electrical isolation by creating separate substrate regions that are electrically isolated from each other. This dimensional separation in the electrical domain allows multiple bias levels to coexist in the same physical substrate area, resolving the complexity of bias application while maintaining compact device size.
Data Source
AI summary
A semiconductor structure includes a core layer; a passive component disposed within the core layer; and a first redistribution layer disposed over the core layer, wherein the first redistribution layer includes a first interconnect, a second interconnect, and a third interconnect disposed between and electrically isolated from the first interconnect and the second interconnect. The third interconnect is electrically connected to the passive component, and at least one of the first interconnect and the second interconnect is electrically isolated from the passive component. A method of manufacturing the semiconductor structure includes providing a first bias between the first interconnect and the second interconnect, providing a second bias to the passive component through the third interconnect, wherein the first bias is greater than the second bias.