Interposer Structure With Embedded Passives for Dense I/O Packaging
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies due to smaller packaging sizes and more integrated functions poses challenges in die packaging, particularly in redistributing I/O pads to a larger area effectively.
Innovation Solution
The implementation of a system-on-wafer assembly that includes a wafer scale interposer with integrated passive devices and a redistribution structure, allowing for heterogeneous integration with short interconnects, symmetrical molding, and miniaturized voltage regulator modules, along with integrated fan-out packages and Pulse Width Modulation circuits, to enhance electrical performance and computing power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area available for I/O pads is decreased to accommodate smaller packaging sizes, then the packaging density is improved, but the number of I/O pads that can be effectively redistributed is reduced
Solution Approach 1:
The patent extends the redistribution of I/O pads from a two-dimensional surface layout to a three-dimensional structure by forming conductive vias that penetrate through the substrate. This allows I/O pads to be redistributed not only across the surface area but also through the vertical dimension, effectively increasing the total number of accessible I/O pads without increasing the packaging footprint.
Solution Approach 2:
The patent implements a nested structure where conductive vias are formed within the substrate, creating hierarchical levels of interconnection. The vias are nested within the substrate material, allowing multiple layers of I/O pad redistribution to be stacked vertically, thereby maximizing the use of available space and increasing packaging density while maintaining high I/O pad counts.
2Adaptability or versatility
If the density of I/O pads is increased to accommodate more functions in smaller areas, then the functional integration is improved, but the difficulty of die packaging and I/O pad redistribution increases
Solution Approach 1:
The patent introduces an intermediary substrate structure that mediates between the high-density I/O pads on the die and the external packaging environment. The substrate with its embedded conductive vias acts as an intermediate redistribution layer, simplifying the packaging process by providing pre-formed, organized interconnection paths that reduce the complexity of directly handling and routing high-density I/O pads.
Solution Approach 2:
The patent segments the I/O pad redistribution function into separate modular components: the die with high-density pads, the substrate with conductive vias, and the external packaging interface. This segmentation allows each component to be optimized independently and assembled systematically, reducing the overall complexity of die packaging while maintaining high functional integration.
Data Source
AI summary
A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.