Embedded Passive Semiconductor Package for Dense Chip Integration
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Solution Overview
Problem
The challenge lies in creating compact semiconductor packages with improved electrical characteristics, particularly in efficiently integrating multiple semiconductor chips and passive devices within a reduced footprint, while managing the complexity of solder ball attachment and testing, and ensuring effective electrical connectivity.
Innovation Solution
The semiconductor package design incorporates a substrate with interconnection layers, passive devices, and a mold layer, featuring a passive device chip embedded within the substrate, which reduces the package size and allows for shorter electrical connection paths between chips and the passive device, utilizing a flip-chip configuration and insulating layers for efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the semiconductor chip is reduced to increase integration density, then the integration density is improved, but it becomes increasingly difficult to attach solder balls and handle testing
Solution Approach 1:
The patent transitions from a traditional planar PCB layout to a 3D stacked architecture where semiconductor chips are vertically stacked and connected through substrate vias. This dimensional change allows multiple chips to be integrated in the vertical direction, achieving high integration density without reducing individual chip size, thereby maintaining ease of solder ball attachment and testing on each chip.
Solution Approach 2:
The patent embeds passive devices within recesses formed in the substrate, creating a nested structure where passive devices are integrated inside the substrate volume rather than occupying surface area. This nesting approach increases integration density while keeping the package footprint compact and maintaining standard chip sizes for ease of manufacturing.
2Reliability
If a fan-out panel level package is used to increase redistribution structure area, then the electrical characteristics are improved, but the package area becomes excessively large
Solution Approach 1:
The patent implements electrical redistribution and interconnection in the vertical dimension through multiple interconnection layers and substrate vias, rather than expanding the horizontal area through fan-out structures. This 3D interconnection approach achieves excellent electrical characteristics with compact package dimensions by utilizing the third dimension for signal routing.
Solution Approach 2:
The patent employs periodic alternating current (AC) coupling through capacitive structures formed between adjacent interconnection layers separated by insulating layers. This periodic capacitive coupling enables high-frequency signal transmission with controlled impedance, achieving superior electrical characteristics for high-speed applications without requiring large fan-out areas.
3Reliability
If multiple interconnection layers are added to improve electrical connectivity, then the electrical characteristics are improved, but the device complexity increases
Solution Approach 1:
The substrate serves multiple functions simultaneously: it provides mechanical support, contains embedded passive devices in recesses, forms capacitive coupling structures between interconnection layers, and provides electrical interconnection through vias and conductive paths. This multi-functionality reduces overall device complexity by consolidating multiple functions into a single substrate structure rather than requiring separate components.
Solution Approach 2:
The patent combines passive devices, interconnection structures, and capacitive coupling elements into an integrated substrate architecture. The insulating layers serve dual purposes as both electrical isolation between conductive layers and as dielectric material for capacitive coupling. This merging of functions reduces the number of discrete components and simplifies the overall device structure.
Data Source
AI summary
An example semiconductor package includes a substrate, a first semiconductor chip mounted on the substrate, a mold layer on the substrate to cover the first semiconductor chip, and outer terminals positioned below the substrate. The substrate includes a first interconnection layer, a second interconnection layer on the first interconnection layer, a passive device mounted on a bottom surface of the second interconnection layer, and a connection member at a side of the passive device and between the first interconnection layer and the second interconnection layer to connect the first interconnection layer to the second interconnection layer. The outer terminals are coupled to a bottom surface of the first interconnection layer, the passive device includes a first pad on a top surface of the passive device, and an interconnection pattern of the second interconnection layer contacts the first pad.