Redistribution Substrate Layout for Embedded Passive Package Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving a reduced size while maintaining reliability and durability, particularly in the integration of semiconductor chips and passive devices like capacitors within the redistribution substrate.
Innovation Solution
The semiconductor package incorporates a redistribution substrate with a dielectric layer, conductive patterns, and seed patterns that allow for the vertical overlap of semiconductor chips with capacitors, reducing size and enhancing reliability through optimized electrical paths and structural design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips and passive devices are integrated within the redistribution substrate, then device functionality is improved, but package size increases
Solution Approach 1:
The patent embeds passive devices (capacitors, resistors) directly within the redistribution substrate structure. The passive devices are formed inside trenches or recesses of the substrate, with conductive patterns and dielectric layers nested around them, creating a compact integrated structure that reduces overall package size while maintaining full functionality
Solution Approach 2:
The patent transitions from planar integration to three-dimensional vertical integration. Multiple layers of conductive patterns, dielectric layers, and passive devices are stacked vertically within the substrate thickness, utilizing the Z-dimension to accommodate more components without increasing the package footprint
2Reliability
If multiple layers of conductive patterns and dielectric layers are added to the redistribution substrate, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the redistribution substrate into multiple discrete layers, each performing specific functions. Conductive patterns are segmented into separate metal layers (first conductive pattern, second conductive pattern, third conductive pattern) with dielectric layers in between, allowing independent fabrication and inspection of each layer while ensuring reliable electrical connectivity
Solution Approach 2:
The patent incorporates passive devices and conductive patterns into the substrate during the substrate fabrication process itself, before the semiconductor chip is mounted. Seed patterns are formed preliminarily in the substrate, and conductive patterns are built up in subsequent processing steps, establishing the electrical interconnection network in advance to simplify final assembly
Data Source
AI summary
Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.