Embedded Passive Substrate Layout for PDN Routing Flexibility
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Solution Overview
Problem
The increasing complexity of integrated circuits and the demand for smaller, cost-effective, and high-performance mobile devices pose challenges in power distribution network (PDN) performance due to the limitations in routing options and the need for additional layers in the package substrate when embedding passive components.
Innovation Solution
The solution involves embedding a passive electronic component within a central core dielectric layer of a substrate and adding thin dielectric build-up layers on top and bottom, allowing for conductive paths directly above and below the passive component, thereby enhancing routing flexibility and reducing the length of conductive paths to improve PDN performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive components are embedded within the package substrate, then PDN performance is improved, but routing options are limited and more layers are required
Solution Approach 1:
The patent embeds passive components within the core substrate rather than placing them only on surface layers, utilizing the third dimension (vertical embedding) to resolve the contradiction. This allows routing to occur in multiple dimensions - both on surface layers and through embedded vias - thereby improving PDN performance without proportionally increasing the number of surface layers required.
Solution Approach 2:
The passive components are nested within the core substrate structure, with dielectric material surrounding the passive components. This nesting approach allows the passive components to be integrated into the substrate itself rather than adding separate layers, improving PDN performance while minimizing increases in overall device complexity.
2Reliability
If passive components are embedded within the package substrate, then PDN performance is improved, but routing flexibility is reduced
Solution Approach 1:
The substrate is segmented into distinct regions: embedded passive component regions within the core, and separate routing regions on the surface layers. This segmentation allows independent optimization - passive components are embedded where needed for PDN performance, while routing flexibility is maintained on the surface layers through traditional PCB routing techniques.
Solution Approach 2:
By embedding passive components in the vertical dimension within the core substrate, the patent frees up horizontal routing space on the surface layers. This dimensional separation maintains routing flexibility on the surface while achieving improved PDN performance through the embedded components.
3Reliability
If more interconnect layers are used to support increased number of devices, then electrical connections are improved, but manufacturing complexity increases
Solution Approach 1:
Passive components are nested within the core substrate, allowing interconnect layers to be formed around them. This nested structure enables electrical connections to embedded components without requiring separate manufacturing processes for each connection, as the embedding process itself creates the interconnect pathways.
Solution Approach 2:
The passive components are embedded in the core substrate before the final interconnect layers are formed. This preliminary action establishes the foundation for electrical connections early in the manufacturing process, simplifying subsequent layer formation and reducing overall manufacturing complexity.
Data Source
AI summary
A device includes a core including an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer contacting the upper core dielectric layer and the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device includes an upper laminate stack coupled to the upper core dielectric layer. The upper laminate stack includes upper metal layers and contact pads configured to electrically connect a die to the passive electronic component by way of conductive paths defined by the set of upper metal layers. The device includes a lower laminate stack coupled to a bottom surface of the lower core dielectric layer. The lower laminate stack includes lower metal layers and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.