Embedded Passive Elements in Semiconductor Die via Through-Hole Vias
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Solution Overview
Problem
In semiconductor devices, long electrical connection paths between active and passive circuitry reduce electrical performance, especially in high-frequency applications, and mounting passive circuit elements on printed circuit boards limits miniaturization and increases area consumption.
Innovation Solution
The integration of conductive through-hole vias (THVs) within the semiconductor die, interconnected with passive circuit elements, reduces conduction paths and enhances electrical performance by embedding passive circuit elements within the die, eliminating the need for through-silicon vias in the active area and minimizing board space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If passive circuit elements are mounted on printed circuit board, then electrical connection path is long, but area consumption increases and miniaturization is limited
Solution Approach 1:
The patent merges passive circuit elements (inductors, capacitors, resistors) directly onto the semiconductor die, combining functions that were previously separated across different components and substrates. This integration shortens electrical connection paths by eliminating external PCB mounting and reduces board space consumption by embedding components within the die footprint.
Solution Approach 2:
The patent transitions from two-dimensional PCB mounting to three-dimensional integration by forming passive circuit elements within multiple insulating layers above the semiconductor die, connected through vertical via structures. This vertical stacking approach minimizes lateral board space while maintaining electrical functionality.
2Ease of manufacture
If through hole vias are drilled in active area or saw streets, then conductive interconnection is achieved, but wafer and die damage occurs
Solution Approach 1:
The patent extracts the via formation process from the active die area and relocates it to the periphery region. Conductive through-hole vias are formed exclusively in the periphery region outside the active area, eliminating mechanical damage to the active die structures while maintaining the essential function of conductive interconnection between stacked dies.
Solution Approach 2:
The periphery region serves as an intermediary zone that provides mechanical support and conductive interconnection functionality without interfering with the active die area. This intermediary region absorbs the mechanical stress of via drilling and bonding processes while protecting the sensitive active circuits.
3Reliability
If passive circuit elements are integrated within semiconductor die, then conduction paths are shortened and electrical performance improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device into distinct functional regions: active area for transistors and periphery region for passive elements. This segmentation allows independent optimization and manufacturing of different circuit functions, reducing overall manufacturing complexity despite the integrated structure.
Solution Approach 2:
The insulating layers serve multiple functions simultaneously: they provide electrical isolation between conductive elements, serve as substrates for forming passive circuit elements, and provide mechanical support for via structures. This multi-functionality reduces the need for additional specialized layers and processes.
Data Source
AI summary
A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.