Embedded Passive Device Vertical Branch Electrode Structure
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Solution Overview
Problem
Conventional embedded capacitor structures face challenges in achieving high capacitance due to the close proximity of source and ground electrodes, leading to unintended conductivity during lamination, and difficulties in controlling the thickness of high-k dielectric layers, which affects the reliability and yield of the manufacturing process.
Innovation Solution
The source and ground electrodes are formed at the same level on the substrate, with vertically arranged branches inside the dielectric layer, using an electroplating process to create trace wiring without etching, and roughening the electrode surfaces for improved adhesion, allowing for a high-density laminate structure with increased capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the source electrode and ground electrode are placed close to each other to increase capacitance, then the capacitance value increases, but unintended conductivity occurs during lamination
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional vertical stacking structure. Multiple capacitor units are stacked in the vertical direction (Z-axis) with alternating source and ground electrodes separated by dielectric layers. This dimensional change allows electrodes to be closer in the vertical dimension while maintaining horizontal separation, thereby increasing capacitance without causing unintended conductivity during lamination.
2Quantity of substance
If an ultra-thin dielectric layer is used to increase capacitance density, then the capacitance per unit area increases, but manufacturing difficulty and yield reduction occur
Solution Approach 1:
The patent divides the capacitor structure into multiple discrete capacitor units stacked in series. Each unit consists of a source electrode, dielectric layer, and ground electrode. This segmentation allows the use of moderate-thickness dielectric layers in each unit while achieving high overall capacitance through the cumulative effect of multiple units, thereby reducing manufacturing difficulty and improving yield compared to using a single ultra-thin dielectric layer.
3Manufacturing precision
If photoresist technology and etching are used multiple times to form embedded resistors, then the resistor structure is achieved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of embedded passive devices (capacitors and resistors) with the standard PCB lamination process. The copper foils are attached to the inner surfaces of pre-laminated core boards, and the passive devices are formed through a unified process sequence that integrates etching, plating, and lamination steps. This merging approach reduces the number of separate processing stages compared to conventional methods that require multiple discrete photoresist and etching cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents unintended conductivity between electrodes, enhances bonding, and significantly increases capacitance density by optimizing the arrangement and material properties, resulting in a capacitance that is more than triple that of conventional methods.
Implementation Method 1
uses an electroplating process to create trace wiring without etching
Implementation Method 2
roughening the electrode surfaces for improved adhesion
Implementation Method 3
vertically arranged branches inside the dielectric layer
Data Source
AI summary
A manufacturing method for mainly embedding the passive device structure in the printed circuit board is presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.