Embedded Passive Devices Using Thick Passivation Over Redistribution Lines

The patent utilizes the vertical dimension by forming a thick passivation layer that extends upward from the substrate surface. This thick layer (greater than traditional thin passivation layers) creates additional vertical space for embedding passive devices such as capacitors, inductors, and resistors. By moving from a two-dimensional planar embedding approach to a three-dimensional vertical embedding approach, the patent increases the volume available for passive devices without increasing the die area, thereby resolving the contradiction between component quantity and available area.

The patent divides the manufacturing process into distinct sequential stages: first forming the thick passivation layer, then patterned etching to create cavities, followed by separate formation of different passive devices (capacitors, inductors, resistors) in different regions, and finally planarization. This segmentation of the complex manufacturing process into manageable discrete steps makes the overall process more controllable and implementable, resolving the contradiction between increased device integration and process complexity.

The patent performs preliminary actions by first forming the thick passivation layer with predetermined thickness and properties before embedding the passive devices. The passivation layer is formed with controlled thickness and material properties that facilitate subsequent device embedding. Additionally, cavities are pre-formed through patterned etching at specific locations where passive devices will be embedded. These preliminary actions establish a prepared substrate that simplifies the subsequent device embedding process and reduces precision requirements during the actual device formation stage, thereby resolving the contradiction between reduced external attachments and manufacturing precision requirements.