Embedded PCB System Module for Wearable Miniaturization
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Solution Overview
Problem
Conventional semiconductor packaging solutions, such as ePOP, face challenges in reducing size and improving power and signal integrity for wearable electronic devices, which limits the miniaturization and efficiency of mobile computing devices.
Innovation Solution
A system module design that embeds a processor chip or PMIC within a printed circuit board (PCB) and connects a semiconductor package using stack balls, allowing for reduced thickness and size while maintaining power and signal integrity through optimized chip placement and voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packaging is used, then device protection and basic functionality are maintained, but the size and thickness of wearable electronic devices cannot be reduced
Solution Approach 1:
The patent embeds the first semiconductor chip (PMIC or processor) directly within the PCB structure, nesting it inside the board rather than mounting it on the surface. This nesting approach reduces the overall device volume and thickness while maintaining reliable electrical connections through embedded vias and conductive paths, thereby resolving the contradiction between size reduction and power/signal integrity maintenance.
Solution Approach 2:
The patent transitions from traditional surface-mount or through-hole mounting (2D placement) to embedded positioning within the PCB thickness (3D integration). The first semiconductor chip is positioned at a first position within the PCB, while the second chip is disposed at a second position, creating a vertical stacking arrangement that reduces the device footprint and thickness while maintaining functional reliability through optimized interconnections.
2Volume of moving object
If ePOP design is used, then device size is reduced, but power line length and complexity increase affecting power integrity
Solution Approach 1:
The patent extracts the power management function by embedding the PMIC (power management integrated circuit) directly within the PCB structure, separating it from the processor chip. This extraction allows for optimized power distribution architecture where the PMIC can be positioned close to power entry points and voltage regulation points, reducing power line length and minimizing power loss while maintaining reduced device thickness through the embedded configuration.
Solution Approach 2:
The patent applies local quality optimization by positioning the first semiconductor chip (PMIC) at a specific first position within the PCB and the second chip at a second position, tailored to optimize power distribution locally. This localized positioning strategy minimizes power line lengths in critical areas while maintaining overall device compactness, thereby reducing power loss without compromising the thickness reduction achieved through ePOP design.
3Adaptability or versatility
If multiple chips are mounted on PCB surface, then functionality is achieved, but device thickness increases
Solution Approach 1:
The patent embeds multiple semiconductor chips within the PCB structure rather than mounting them on the surface. The first semiconductor chip is embedded in the PCB at a first position, and the second semiconductor chip is disposed at a second position within the PCB. This nesting approach maintains full device functionality while significantly reducing the overall system module thickness compared to traditional surface-mount configurations.
Solution Approach 2:
The patent transitions from 2D surface mounting to 3D embedded positioning within the PCB. By disposing chips at different positions within the board thickness rather than on the surface, the design achieves versatile functionality with multiple chips while reducing the overall device thickness, effectively utilizing the third dimension for component placement optimization.
Data Source
AI summary
A system module includes a printed circuit board (PCB), a first semiconductor chip embedded in the PCB, a semiconductor package connected to the PCB through a plurality of stack balls, and a second semiconductor chip disposed on a surface of the PCB in a space between the PCB and the semiconductor package.