Embedded Photodetector in 3D CMOS Stacked Chip
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Solution Overview
Problem
High-speed silicon photodetectors in CMOS-based optical receivers face bandwidth limitations due to deep carrier generation and long transit times, while modifications to the CMOS process to address this issue are costly and difficult to manufacture, and unmodified CMOS photodetectors have low efficiency.
Innovation Solution
An embedded photodetector apparatus with a thinned CMOS layer structure, including a bulk substrate with a buried oxide layer and a silicon-on-insulator layer, featuring laterally arranged interdigitated p+ and n+ contacts, which allows for efficient absorption of 850 nm light and quick carrier collection, maintaining high bandwidth without significant changes to the existing CMOS process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a lateral interdigitated structure is used in standard CMOS process, then manufacturing cost is reduced and ease of manufacture is improved, but bandwidth is limited due to long carrier transit time
Solution Approach 1:
The patent transitions from a lateral interdigitated structure to a vertical stacked structure, changing the spatial dimension of carrier collection. The p+ and n+ contacts are arranged vertically through the silicon layer thickness, reducing carrier transit distance from lateral to vertical path and enabling faster bandwidth while maintaining compatibility with standard CMOS processes
2Speed
If the CMOS process is modified to block deep carriers, then bandwidth is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the problematic deep carrier collection path by using a vertical PIN structure where the intrinsic layer is positioned to prevent deep carrier generation. This removes the source of long transit time carriers while maintaining a simple process flow that does not require modifications to standard CMOS manufacturing
3Productivity
If a vertical PIN structure with thinned CMOS layer is used, then absorption efficiency is improved and bandwidth is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary thinning of the CMOS layer to the optimal thickness range (2-15 μm) before photodetector fabrication. This preliminary action ensures that the subsequent vertical PIN structure achieves optimal absorption efficiency while maintaining manufacturability, as the thinning is done using standard CMOS thinning processes rather than requiring precision control during photodetector fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a good tradeoff between bandwidth and efficiency, enabling high-speed data communication with improved absorption efficiency and reduced reliance on deep carriers, while being compatible with existing optical packaging technology.
Implementation Method 1
the active photodiode area being receptive of an optical signal incident thereon
Implementation Method 2
a buried oxide (BOX) layer disposed adjacent to the active photodiode area substrate
Implementation Method 3
laterally arranged interdigitated p+ and n+ type contacts of a PIN photodetector extending through the BOX layer to the active photodiode area substrate
Data Source
AI summary
An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein.


