Embedded Photosensitive Chip Substrate for Compact Packaging
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Solution Overview
Problem
Conventional packaging substrates with photosensitive semiconductor chips are bulky and complex to fabricate due to the need for conductive through holes and a surrounding dam, which increases size and height, making them unsuitable for compact electronic devices and complicates the fabrication process.
Innovation Solution
A packaging substrate with an embedded photosensitive semiconductor chip is fabricated by embedding the chip in a core board with conductive through holes, eliminating the need for external conductive wires and a dam, using a through cavity in the core board and an adhesion layer with a light-permeable window to expose the photosensitive portion, and forming a circuit layer with conductive vias for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive through holes and a dam are used in the conventional packaging substrate structure, then electrical connection and chip protection are achieved, but the substrate size and height increase, making it unsuitable for compact electronic devices
Solution Approach 1:
The patent removes the dam structure from the packaging substrate. Instead of using a dam to protect the chip and provide electrical connection, the invention embeds the chip directly into the substrate with conductive vias passing through the substrate to establish electrical connections, thereby eliminating the need for a dam and reducing overall substrate height and volume.
Solution Approach 2:
The patent transitions from a planar mounting structure to a three-dimensional embedded structure. The chip is embedded within the substrate volume rather than being mounted on the surface, and conductive vias extend through the substrate thickness to provide electrical connections, utilizing the vertical dimension to reduce the horizontal footprint and overall package size.
2Stability of the object's composition
If the core board is made thicker to maintain stability and prevent warpage, then structural stability is improved, but the fabrication process becomes more complex and the substrate cannot meet compact size requirements
Solution Approach 1:
The patent performs preliminary actions during substrate fabrication by forming conductive vias and embedding the chip before final substrate consolidation. The chip embedding and electrical connection establishment are integrated into the substrate manufacturing process itself, allowing the substrate to achieve its final thickness and structural stability without requiring subsequent complex assembly steps or dam formation processes.
3Reliability
If space is reserved for the dam and conductive wires are used for electrical connection, then chip electrical connection is achieved, but the overall planar size and height of the packaging substrate increase
Solution Approach 1:
The patent merges the electrical connection function and mechanical support function into the substrate itself. Conductive vias are formed directly through the substrate material, eliminating the need for separate wire bonding or trace routing on the substrate surface. This integration reduces the planar area required for electrical connections and eliminates the need for additional height-consuming wire bonds or dams.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces the substrate's size and height, and prevents warpage, enabling the creation of a compact-sized packaging substrate suitable for miniaturized electronic products.
Implementation Method 1
an adhesion layer having a light-permeable window for exposing the photosensitive portion of the semiconductor chip
Implementation Method 2
a plurality of conductive through holes for electrically connecting the first and second electrode pads
Data Source
AI summary
A packaging substrate with an embedded photosensitive semiconductor chip and a method for fabricating the same are provided. The method includes the steps of: disposing the semiconductor chip in an through cavity of a core board with the photosensitive portion of the semiconductor chip being exposed from the through cavity; forming a first circuit layer on the core board at a side opposite to the photosensitive portion so as to electrically connect the electrode pads of the semiconductor chip; and forming a light-permeable layer on the core board at the same side with the photosensitive portion via an adhesion layer so as to allow light to penetrate through the light-permeable layer and reach the photosensitive portion of the semiconductor chip. When fabricated by the method, the packaging substrate dispenses with conductive wires and a surrounding dam and thus is efficiently downsized.