Embedded Digital PHY Standby for Low-Power Automotive Ethernet SoCs
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Solution Overview
Problem
Automotive Ethernet networks face challenges in reducing power consumption and latency during state transitions due to the increasing number of electronic control units, with existing protocols not effectively addressing the need for an intermediate power state between sleep and wake states.
Innovation Solution
Implementing a system-on-chip (SoC) with an always-on power domain and switched power domain, utilizing a low-frequency clock during standby mode and a high-frequency clock during active mode, along with a power manager to control state transitions, enabling a low-power standby state compatible with existing Ethernet standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the SoC transitions to a sleep state to reduce power consumption, then power usage is reduced, but the transition latency increases and responsiveness deteriorates
Solution Approach 1:
The patent implements a dynamic power management system that transitions the SoC between three states (sleep, standby, wake) based on operational needs. The standby state serves as a dynamic intermediate state that the system can quickly enter and exit, providing adaptive power consumption control without the high latency penalty of full sleep transitions.
Solution Approach 2:
The standby state acts as an intermediary state between sleep and wake states. This intermediate state allows the system to maintain partial operational capability while consuming reduced power, serving as a buffer that reduces transition latency when full wake functionality is needed.
2Loss of energy
If the SoC enters a deep sleep state to minimize power consumption, then energy efficiency improves, but the system complexity increases due to additional state management requirements
Solution Approach 1:
The patent segments the power management system into distinct functional domains: an always-on power domain that remains active and a switched power domain that can be powered down. This segmentation allows independent control of different system components, simplifying overall state management while achieving deep power savings.
Solution Approach 2:
The system dynamically adjusts power domain states based on operational requirements, transitioning between sleep, standby, and wake states as needed. This dynamic approach allows the system to optimize energy efficiency without requiring complex manual state management, as the transitions are automatically controlled based on system conditions.
3Speed
If the PHY controller remains active during standby mode to maintain responsiveness, then transition speed improves, but power consumption increases
Solution Approach 1:
The patent extracts the PHY controller from the main SoC power management cycle by placing it in a separate always-on power domain. This extraction allows the PHY controller to remain active and responsive during standby mode while the rest of the SoC enters a low-power state, achieving fast transition speeds without proportionally increasing overall power consumption.
Solution Approach 2:
The system segments power consumption by creating separate power domains: the PHY controller resides in an always-on domain that maintains minimal activity for fast response, while the main SoC is in a switched power domain that can be fully powered down. This segmentation enables differential power management that optimizes both transition speed and power consumption.
Data Source
AI summary
An automotive Ethernet system-on-chip (SoC) implements a power management state that is a lower power standby for an embedded controller of a physical layer (PHY). The SoC combines an always-on power domain (AON) and a switched power domain (SWP). A power manager activates the lower power standby state through a standby signal sent to a power controller in the AON. The standby state enables the power manager of the SoC to switch a system clock from a high-frequency clock to a low frequency clock generated in the AON and turns off a clock dedicated to the PHY.