Embedded PHY IP Core for FPGA Testing
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Solution Overview
Problem
Current FPGA testing devices with high-speed physical layers are inadequate for validating devices requiring low-speed physical layers, leading to increased costs, limited scalability, and delayed market entry due to the need for external low-speed PHY chips and limited I/O capabilities.
Innovation Solution
An embedded physical layer (EPHY) for FPGAs that can handle both high-speed and low-speed physical layers, incorporating a logic portion and glue hardware with differential amplifiers and multiplexers to support various speeds and protocols, allowing for flexible updates without requiring ASIC production cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an external low-speed PHY chip is used to test devices requiring low-speed PHYs, then the testing capability is improved, but the system cost and complexity increase
Solution Approach 1:
The patent merges the low-speed PHY functionality into the FPGA device itself by utilizing existing high-speed PHY infrastructure. The high-speed PHY's transceiver is configured to operate at lower speeds through software control, eliminating the need for separate external low-speed PHY chips and reducing system complexity while maintaining testing capability.
Solution Approach 2:
The high-speed PHY transceiver is designed to serve multiple functions by operating at different speed modes. It can function as both high-speed and low-speed PHYs depending on configuration, making it a universal interface that supports various testing requirements without requiring dedicated hardware for each speed tier.
2Adaptability or versatility
If an external low-speed PHY chip is used, then low-speed testing is enabled, but the I/O count and BOM cost increase
Solution Approach 1:
The patent combines the functionality of multiple PHY chips into a single integrated PHY interface within the FPGA. By configuring the high-speed PHY to support both high and low speed modes, the system eliminates the need for separate external low-speed PHY chips, thereby reducing the total I/O count and BOM cost while maintaining low-speed testing capability.
3Adaptability or versatility
If ASIC PHY design is used for next generation, then future speed support is achieved, but time-to-market is delayed
Solution Approach 1:
The patent implements dynamic speed configuration capability in the existing high-speed PHY through software control. This allows the PHY to adapt its operating speed based on testing requirements without requiring hardware changes or ASIC redesign. Consequently, the system can support current and future speed generations through software updates alone, eliminating time delays associated with ASIC production cycles while maintaining forward compatibility.
4Speed
If high-speed PHY only is used in FPGA, then high-speed performance is achieved, but low-speed device validation is prevented
Solution Approach 1:
The patent enables dynamic speed adaptation in the PHY interface by configuring the high-speed PHY to operate at different speed modes through software control. This dynamic reconfiguration allows the same physical interface to support both high-speed and low-speed operations, maintaining high-speed performance capability while enabling low-speed device validation without requiring separate hardware paths.
Data Source
AI summary
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.