Embedded Polysilicon Resistor in Replacement Gate Process
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Solution Overview
Problem
Incorporating unsilicided polysilicon resistors into conventional replacement gate processes for high-k metal gate transistors is cumbersome, requiring additional photomasks and leading to variability in resistance values due to chemical-mechanical polishing and silicidation challenges.
Innovation Solution
A polysilicon resistor structure is formed within a trench in the silicon surface during dummy gate polysilicon deposition, with interlevel dielectric material protecting it from subsequent processes, allowing for efficient heat dissipation and simplified fabrication without additional critical photolithography masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If polysilicon resistors are incorporated into conventional replacement gate processes, then resistor functionality is achieved, but fabrication complexity increases due to additional photomasks and process steps
Solution Approach 1:
The patent merges the formation of polysilicon resistors with the existing dummy gate structure formation process. The same polysilicon deposition and patterning steps used to create dummy gates are utilized to form resistor regions, eliminating the need for separate photomasks and process steps dedicated solely to resistor fabrication.
Solution Approach 2:
The polysilicon structures serve dual functions: as dummy gates for transistor formation and as resistor elements. By making the polysilicon deposition and patterning process universal, the same structures can function as either dummy gates or resistors depending on their location and configuration in the circuit layout.
2Manufacturing precision
If chemical-mechanical polishing is applied to planarize the surface, then surface flatness is improved, but resistance value variability increases due to polysilicon removal
Solution Approach 1:
The patent applies different treatments to different regions: dummy gate polysilicon structures are planarized by CMP while resistor polysilicon regions are protected or selectively processed. This local differentiation ensures that resistor regions maintain their original thickness and resistance characteristics while still achieving overall surface planarity for subsequent processing steps.
3Manufacturing precision
If additional photomasks are used to define resistor regions, then resistor placement precision is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent performs preliminary patterning of polysilicon regions during the dummy gate formation stage, before dedicated resistor processing would normally occur. By pre-defining resistor locations using the same photomasks required for transistor layout, placement precision is achieved without adding extra critical photolithography steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient resistive heat dissipation and compatible integration with high-k metal gate replacement gate processes, reducing fabrication complexity and variability in resistance values.
Implementation Method 1
interlevel dielectric material protecting it from subsequent processes
Implementation Method 2
enables efficient resistive heat dissipation
Data Source
AI summary
An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.