Embedded Power Die Vias for Thermal Dissipation
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Solution Overview
Problem
SMD-based power electronics face challenges with cooling capabilities, leading to increased die costs and inefficiencies due to large gate pad sizes and difficulties in supporting thin semiconductor dies, which result in electrical problems.
Innovation Solution
A semiconductor package design featuring an insulating substrate with embedded power semiconductor dies and electrically conductive vias that form solderable contact pads, allowing for direct copper-to-copper connections and improved thermal dissipation, while maintaining a smaller form factor and supporting thin dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a can/lid approach is used to provide low thermal resistance and top-side cooling, then thermal performance is improved, but gate pad size increases reducing active area and increasing die cost
Solution Approach 1:
The patent transitions from planar gate pad connections to three-dimensional vertical vias that extend through the insulating substrate. This dimensional change allows thermal management and electrical connections to occur in the vertical dimension rather than requiring expanded horizontal gate pad area, thereby maintaining small gate pad sizes while achieving low thermal resistance through the substrate thickness.
Solution Approach 2:
The vias structure serves multiple functions simultaneously: it provides electrical connection for the gate terminal, establishes thermal pathways for heat dissipation, and enables compact packaging. This multi-functionality eliminates the need for separate dedicated thermal management structures that would increase gate pad size, as the same via structures handle both electrical and thermal requirements.
2Temperature
If a can/lid approach is used for thermal management, then cooling capability is improved, but bond line thickness issues arise with thin semiconductor dies due to thermal material creepage
Solution Approach 1:
The patent extracts the thermal management function from the can/lid structure and implements it through separate vertical vias filled with thermally conductive material. This extraction eliminates the creepage problem by preventing thermal material from contacting the sidewalls of thin dies, as the via structure provides contained vertical pathways that do not require lateral adhesion to die sidewalls.
Solution Approach 2:
The patent introduces an intermediary via structure that mediates between the gate terminal and the insulating substrate. This via structure with controlled fill material provides a reliable thermal and electrical connection pathway without requiring direct contact with die sidewalls, thereby preventing creepage-related electrical problems while maintaining effective thermal management.
3Temperature
If large gate pad size is used for can/lid connections, then thermal resistance is reduced, but active area decreases increasing die cost
Solution Approach 1:
The patent moves thermal management from the horizontal plane to the vertical dimension by implementing thermal pathways through vias that extend through the substrate thickness. This allows heat dissipation to occur vertically without requiring expanded horizontal gate pad area, thereby maintaining high active area while achieving low thermal resistance through optimized via dimensions and thermal material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances thermal performance, reduces die costs, and supports thin semiconductor dies by providing direct pad contact and improved thermal dissipation, addressing the inefficiencies and electrical issues of existing SMD-based power electronics.
Implementation Method 1
electrically conductive first vias extending through the insulating substrate... providing direct pad contact and improved thermal dissipation
Implementation Method 2
solderable first contact pads at the second main side of the insulating substrate and formed by the first vias... enhanced thermal performance
Data Source
AI summary
A semiconductor package includes: an insulating substrate having opposing first and second main sides; a power semiconductor die embedded in, and thinner than or a same thickness as, the substrate, and including a first load terminal bond pad at a first side which faces a same direction as the substrate first main side, a second load terminal bond pad at a second side which faces a same direction as the substrate second main side, and a control terminal bond pad; electrically conductive first vias extending through the substrate in a periphery region; a first metallization connecting the first load terminal bond pad to the first vias at the substrate first main side; solderable first contact pads at the substrate second main side and formed by the first vias; and a solderable second contact pad at the substrate second main side and formed by the second load terminal die bond pad.