Embedded Power Distribution Network in Chip Interconnect Bridge

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Solution Overview

Problem

Conventional chip interconnect bridge devices lack power distribution wiring, leading to increased IR voltage drop and heating due to longer power/ground trace lengths, as they block power distribution from the package substrate to IC chips with overlapping power/ground pads.

Innovation Solution

Incorporating an embedded power distribution network within the chip interconnect bridge device to distribute positive and negative power supply voltage from the package substrate to IC chips, using high-density wiring and power distribution traces, allowing power to be routed directly to contact pads even under the bridge device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional chip interconnect bridge devices are used without embedded power distribution network, then chip-to-chip interconnect wiring is simplified, but power distribution efficiency deteriorates due to longer power/ground trace lengths causing increased IR voltage drop and heating

Engineering Contradiction:
Improvepower distribution efficiencyVSAvoidbridge device structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the power distribution function with the chip interconnect bridge device by embedding a power distribution network within the bridge device substrate. This integration allows power and ground traces to be routed directly through the bridge device to contact pads on IC chips, eliminating the need for separate power distribution paths and reducing overall trace length. The embedded power distribution network is formed using conductive traces and vias within the bridge device's internal layers, combining interconnect and power distribution functions into a single unified structure.

Inventive Principle:
Principle #5Merging (Combining)

2Length of moving object

If power distribution traces are extended to reach IC chips under the bridge device, then power delivery is improved, but IR voltage drop and heating increase due to longer trace lengths

Engineering Contradiction:
Improvepower/ground trace lengthVSAvoidIR voltage drop and heating
Core Design Contradiction:
Length of moving objectVSLoss of energy

Solution Approach 1:

The patent utilizes the vertical dimension by routing power and ground traces through vias within the bridge device substrate. Instead of extending traces laterally across the bridge device, the embedded power distribution network uses vertical vias to connect different conductive layers, delivering power directly to contact pads on IC chips positioned underneath the bridge device. This three-dimensional trace routing significantly reduces the effective trace length compared to traditional planar routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If an embedded power distribution network is added to the chip interconnect bridge device, then power distribution efficiency is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidbridge device fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The embedded power distribution network is fabricated using standard semiconductor manufacturing processes during the bridge device fabrication sequence. Conductive traces and vias are formed in advance as part of the bridge device's internal structure, before the bridge device is assembled with IC chips. This preliminary formation of power distribution paths integrates seamlessly with existing fabrication workflows, minimizing additional manufacturing steps and complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11133259B2Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network
Publication Date: 2021.09.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11133259B2 patent drawing
  • US11133259B2 patent drawing
  • US11133259B2 patent drawing

AI summary

A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.