Substrate-Embedded Power Grid for Low-Resistance ESD Paths
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Solution Overview
Problem
Semiconductor devices face challenges in handling high current stress during Electrostatic Discharge (ESD) events due to reduced capability and increased resistance in smaller devices, leading to performance degradation and reliability issues.
Innovation Solution
The semiconductor device incorporates a substrate with embedded metal rails and power grids, utilizing high-k dielectric materials and trench-based decoupling capacitors to reduce resistance and enhance ESD performance, while also acting as a heat sink to dissipate heat effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor device size is reduced to enable scaling, then device density and integration are improved, but capability to handle high current stress during ESD events deteriorates
Solution Approach 1:
The patent transitions from planar power grid structures to three-dimensional vertically embedded power grids within the substrate. Multiple power grid layers are stacked at different depths, allowing current to flow through vertical pathways via vias and TSVs (through-silicon vias). This dimensional transformation enables compact ESD protection structures that provide low-impedance discharge paths without occupying additional lateral area, thus maintaining high device density while improving ESD handling capability.
Solution Approach 2:
The patent implements nested ESD protection structures where ESD protection devices are integrated within or adjacent to the vertically stacked power grid layers. The ESD protection circuitry is embedded within the substrate structure itself, with multiple protection devices positioned at different vertical levels corresponding to different power grid layers. This nesting approach allows ESD protection functionality to be incorporated without increasing the overall device footprint, resolving the contradiction between compact size and ESD robustness.
2Area of stationary object
If device size is reduced for scaling, then area efficiency is improved, but resistance in ESD path increases
Solution Approach 1:
The patent creates low-impedance ESD discharge paths by utilizing vertical current flow through multiple stacked power grid layers connected via vias and TSVs. Instead of relying on long lateral metal traces that would be required in planar designs, the vertical stacking enables short, direct current pathways through the substrate thickness. This dimensional approach significantly reduces ESD path resistance while maintaining compact device area.
Solution Approach 2:
The patent merges the power distribution network with the ESD protection network by using the same vertically stacked power grid structure for both functions. The power grid layers serve dual purposes: supplying power to active devices and providing low-impedance discharge paths for ESD events. This consolidation eliminates the need for separate ESD protection traces, reducing overall resistance while maintaining area efficiency.
3Ease of manufacture
If conventional power grid structures are used, then manufacturing simplicity is maintained, but ESD performance and signal integrity deteriorate
Solution Approach 1:
The patent extends conventional planar power grid manufacturing to three dimensions by adding vertical stacking of power grid layers. The fabrication process builds upon standard CMOS backend-of-line (BEOL) metallization techniques, adding alternating layers of conductive materials and dielectric layers in the vertical dimension. This approach maintains manufacturing simplicity by using established processes while achieving superior ESD performance through the low-impedance vertical pathways provided by the stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves ESD performance and reliability by reducing resistance in the ESD path, minimizing heat conduction to signal wires, and enabling high-density routing with improved signal integrity, thus supporting advanced nodes and adhering to Moore's law scaling.
Implementation Method 1
a first high-k dielectric part between the first power line and the first ground line
Implementation Method 2
acting as a heat sink to dissipate heat effectively
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of metal rails embedded in the substrate, and a power grid embedded in the substrate, at least one of the plurality of metal rails being part of the power grid and being directly connected to the substrate to control an Electrostatic Discharge (ESD) in the semiconductor device.