Embedded Power Package Layout for Miniaturization and Upward Cooling
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Solution Overview
Problem
Existing embedded component packaging (ECP) technologies for power modules with high-current requirements face challenges in miniaturization and heat dissipation due to the large size of inductor components, which occupy a significant area and hinder integration when tiled with other components.
Innovation Solution
The solution involves stacking smaller electronic components such as capacitors and resistors in a two-dimensional arrangement with the inductor, using through holes to accommodate components of varying sizes, and altering the heat dissipation path from downward to upward, with interconnect layers and a heat dissipation module to enhance cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If inductor component and other electronic components are tiled in the substrate according to conventional technology, then the structure is simple to manufacture, but a large area is occupied which is not conducive to integration and miniaturization
Solution Approach 1:
The patent transitions from conventional two-dimensional tiling arrangement to a three-dimensional stacked arrangement where smaller electronic components are vertically stacked above larger components on the substrate. This dimensional change allows multiple components to occupy the same footprint area, significantly reducing the overall occupied area while maintaining manufacturing feasibility through vertical integration processes
2Power
If the inductor component size is increased to meet high-current requirements, then the current carrying capacity is improved, but the overall package size increases which hinders miniaturization
Solution Approach 1:
The patent implements a nesting strategy where smaller electronic components are placed within the vertical projection area of the larger inductor component, stacking them above the substrate plane. This allows the inductor to maintain its large size for high-current capability while other components occupy the same horizontal footprint, effectively nesting the component hierarchy to reduce overall package volume
3Ease of manufacture
If electronic components are embedded side by side in the substrate, then the structure is simple and easy to manufacture, but the heat dissipation capability is insufficient for high-current power modules
Solution Approach 1:
The patent moves heat dissipation from a two-dimensional planar configuration to a three-dimensional vertical structure. By stacking components vertically and creating multiple levels, the design increases the surface area available for heat dissipation and enables better thermal management through vertical heat pathways, while maintaining manufacturing simplicity through established stacking processes
Data Source
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AI summary
This application provides an embedded package structure, a power supply apparatus, and an electronic device. First electronic components with smaller sizes are stacked, and then arranged in a substrate frame in a two-dimensional manner with a larger-size inductor component to form an embedded package structure. This can reduce an area occupied by the entire embedded package structure, and reduce an overall size of the structure, thereby facilitating integration and miniaturization. Then, a chip is disposed on the embedded package structure, so that the chip serving as a main heat source is placed on a surface of the power supply apparatus. Compared with an existing power module structure in which a chip is embedded in a substrate to form an ECP module and an inductor is mounted on a surface of the ECP module, in the embedded package structure provided in this application, a main heat dissipation path of the chip is changed from an existing downward heat dissipation direction to an upward heat dissipation direction, which may improve a heat dissipation capability.