Embedded Power Stage Inlays for Compact Vertical Current Packaging
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Solution Overview
Problem
Conventional semiconductor packaging solutions have reached physical limits in improving performance parameters such as power loss, current density, and power consumption in power conversion circuits, particularly in automotive and industrial applications, where high-performance power conversion devices with a small areal footprint and robust electrical interconnections are needed.
Innovation Solution
A power semiconductor module arrangement comprising a circuit carrier with embedded power stage inlays, each consisting of first and second transistor dies and a driver die, connected via conductive connectors through an upper metallization layer, allowing for vertical current flow and efficient space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional semiconductor packaging solutions are used, then manufacturing simplicity is maintained, but performance parameters (power loss, current density, power consumption) cannot be improved beyond physical limits
Solution Approach 1:
The power conversion circuit is divided into multiple independent power stage inlays, each containing transistor dies and driver die. These modular inlays can be independently optimized and manufactured, then assembled into the final circuit carrier, enabling improved performance while managing complexity through modular architecture
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional vertical stacking, with transistor dies and driver die arranged in multiple layers and connected via vertical conductive paths. This vertical integration enables higher current density and reduced power loss by shortening current paths while utilizing spatial volume more efficiently
2Power
If larger area is used for power conversion circuits, then performance parameters can be improved, but areal footprint increases
Solution Approach 1:
By stacking power stage inlays vertically in multiple layers within the circuit carrier, the patent achieves high power conversion capability in a compact footprint. The vertical arrangement allows multiple power stages to occupy overlapping horizontal space at different vertical levels, dramatically increasing power density
Solution Approach 2:
The modular power stage inlays are nested within recesses in the circuit carrier substrate, with each inlay containing tightly integrated transistor dies and driver die. This nested arrangement maximizes space utilization by fitting components into available volumes rather than spreading them out planarly
3Productivity
If more power stage inlays are assembled, then productivity and power conversion capability increase, but device complexity increases
Solution Approach 1:
The circuit carrier is divided into multiple standardized recesses, each accommodating a modular power stage inlay. This segmentation allows independent manufacturing and testing of individual inlays, then systematic assembly into the final circuit, enabling scalable production while managing complexity through standardization
Solution Approach 2:
The power stage inlays are designed as universal modular units that can be interchangeably assembled in different configurations within the circuit carrier. Each inlay serves multiple functions (power switching, driving, and interconnection) and can be arranged in various patterns to meet different power conversion requirements, enhancing productivity through standardized components
Data Source
AI summary
A power semiconductor module arrangement includes a circuit carrier including an electrically insulating substrate and an upper metallization layer disposed on upper side of the electrically insulating substrate, and a plurality of power stage inlays that each include first and second transistor dies and a driver die configured to control switching of the first and second transistor dies. Each of the power stage inlays are modular units comprising terminals that are electrically connected to the first and second transistor dies and the driver die. Each of the power stage inlays is embedded within the electrically insulating substrate. The upper metallization layer comprises conductive connectors that extend over the power stage inlays and connect with the terminals of the terminals of each of the power stage inlays.