Embedded Processor Security via Neutral Instruction Insertion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Embedded processors in SoCs used for safety-critical tasks face security vulnerabilities as attackers can monitor power consumption and core activity to deduce program branches, compromising encryption keys, and existing solutions incur significant hardware overhead.
Innovation Solution
Implementing randomly controlled wait times using neutral, ISA-compliant instructions within the existing debug infrastructure of the processor core, ensuring even distribution and minimal performance impact, thus masking branch information from attackers without substantial hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If randomly controlled wait times are inserted to mask program branches, then security is improved, but performance deteriorates
Solution Approach 1:
The patent implements periodic insertion of neutral instructions at predetermined rates (e.g., 15-30% interruption rate) to mask program branches. This periodic action creates power consumption patterns that do not directly correlate with control flow, thereby improving security against side-channel attacks while maintaining acceptable performance through controlled interruption rates.
2Reliability
If neutral instructions are inserted to overlay program execution, then security is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the processor's existing debug infrastructure and standard instruction set architecture (ISA) to implement security enhancements. By repurposing built-in resources like debug halt mechanisms and existing neutral instructions, the system achieves improved security without adding substantial external hardware complexity.
Solution Approach 2:
The patent employs multi-functional use of existing processor resources. The same debug infrastructure and neutral instructions that could serve debugging purposes are also utilized for security enhancement through random wait time insertion, thereby avoiding additional dedicated hardware for security functions.
3Reliability
If wait times are inserted to prevent branch analysis, then security is improved, but loss of time increases
Solution Approach 1:
The patent dynamically adjusts the interruption rate parameter (set between 15-30%) to balance security enhancement with performance impact. By optimizing this parameter, the system achieves sufficient security improvement while minimizing the time loss from inserted wait instructions.
Data Source
Figure 1
AI summary
The invention discloses a method for increasing security of embedded processors and an apparatus performing the method. The object to provide a method that only needs a slim hardware overhead to increase the security of embedded processors of a SoC and is completely transparent to the core logic of the processor is solved by a method using an existing debug infrastructure of a processor core of the embedded processor, whereas randomly controlled wait times or instructions forming a random signal are inserted in a program code performed by the processor by using neutral instructions that do not affect an actual program code of the processor, and whereas an external logic of the processor core post-processes the random signal to ensure that the random signal is inserted within a pre-determined rate.