Embedded Protocol Analyzer for HDL Simulation Transaction Visualization
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Solution Overview
Problem
Current hardware description language (HDL) simulation tools lack efficient protocol analysis capabilities, making it difficult to visualize and debug transactions between circuit blocks in integrated circuits, as they require post-processing of low-level signals to identify transactions, which is complex and not directly consumable by viewers.
Innovation Solution
Incorporating a protocol analyzer into the circuit design, coupled to low-level signals, which detects transactions and generates transaction data that can be directly output to a viewer, allowing for transaction-level visualization without relying on built-in protocol analysis in simulators or viewers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If post-processing of low-level signals is used to identify transactions, then transaction analysis capability is achieved, but system complexity and processing difficulty increase significantly
Solution Approach 1:
The patent applies preliminary action by embedding the protocol analyzer within the circuit design itself, allowing transaction detection to occur during the simulation process rather than requiring post-processing. The protocol analyzer continuously monitors low-level signals and identifies transactions in real-time, converting them to transaction data that is immediately available for viewing and debugging, thus eliminating the need for complex post-processing operations.
2Ease of operation
If embedded protocol analyzer is used to detect transactions in real-time, then transaction visualization is simplified, but circuit design complexity increases
Solution Approach 1:
The patent employs an intermediary approach by introducing a dedicated protocol analyzer module that acts as a mediator between the low-level signal generation in the circuit design and the high-level transaction visualization. This protocol analyzer translates complex low-level signals into simplified transaction data structures that are easily consumable by viewing tools, thereby simplifying transaction visualization while containing design complexity within a specialized component rather than throughout the entire system.
3Productivity
If transaction data is generated directly during simulation, then debugging efficiency is improved, but computational resources are consumed
Solution Approach 1:
The patent applies the extraction principle by isolating the protocol analysis functionality into a separate, dedicated module within the simulation environment. This protocol analyzer extracts transaction information from the low-level signals generated during circuit simulation, processing only the relevant data needed for transaction identification. By extracting and processing only essential transaction data rather than analyzing all simulation data, the system improves debugging efficiency while minimizing computational resource consumption.
Data Source
AI summary
Protocol analysis can include simulating, using a processor, a circuit design including a protocol analyzer embedded therein. The protocol analyzer can be coupled to low-level signals of an interface of the circuit design. During the simulating, the protocol analyzer detects a transaction from the low-level signals received from the interface. Transaction data is generated by the protocol analyzer specifying the transaction. The transaction data is output from the protocol analyzer.