Embedded Power Rail Structure for 3D Short-Channel Transistors
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling density and effectively suppressing short channel effects while maintaining current control capability, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a base substrate with embedded electrode plates and power rails within an insulating layer, along with gate electrodes and source/drain regions, to enhance electrical connectivity and reduce resistance, allowing for improved scaling and current control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor with three-dimensional channel is used, then scaling density and current control capability are improved, but short channel effect becomes more severe
Solution Approach 1:
The patent introduces a vertical stacking dimension by forming multiple electrode plates (first electrode plate, second electrode plate, third electrode plate) stacked in the vertical direction, creating a three-dimensional channel structure. This dimensional transition from planar to vertical enables higher scaling density while maintaining gate control over the channel through the multi-gate configuration that surrounds the vertical channel.
2Length of moving object
If gate length is not increased, then device scaling is maintained, but current control capability deteriorates
Solution Approach 1:
The patent compensates for the reduced gate length by extending gate control into the vertical dimension through multiple stacked electrode plates. The first, second, and third electrode plates collectively provide gate control over the vertical channel, effectively increasing the total gate-channel interaction area without increasing the planar gate length footprint.
3Reliability
If power rail resistance is reduced, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple electrode plates (first, second, and third electrode plates) into an integrated power delivery structure. These electrode plates are electrically connected through conductive vias and form a unified power rail system that reduces overall resistance while sharing the complexity burden across multiple functional layers rather than requiring a single complex low-resistance path.
Data Source
AI summary
A semiconductor device includes a base substrate, a first electrode plate on the base substrate, a first power rail on the first electrode plate, the first power rail extending in a first horizontal direction and overlapping the first electrode plate in a vertical direction, a second power rail on the first electrode plate, the second power rail extending in the first horizontal direction and overlapping the first electrode plate in the vertical direction, and the second power rail being spaced apart from the first power rail in a second horizontal direction different from the first horizontal direction, a first power rail contact electrically connecting the first electrode plate and the first power rail, an insulating layer on the base substrate to surround the first electrode plate, the first power rail, and the second power rail, and a gate electrode extending in the second horizontal direction on the insulating layer.