Embedded RAM Scan Circuit for Fault Detection

Solution Overview

Problem

Existing methods for testing RAM blocks embedded in integrated circuits are inefficient, requiring numerous pins and wiring or relying on functional tests that cannot effectively observe and control RAM inputs and outputs, limiting the ability to detect faults within these blocks.

Innovation Solution

A RAM scan test method using a scan circuit with flip-flops and a multiplexer that bypasses the RAM block, allowing for serial data loading and observation, enabling internal scan and RAM scan testing with minimal pins and facilitating the use of Automatic Test Pattern Generation tools.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Difficulty of detecting and measuring

If address and data pins are brought out to chip pins for testing, then access to RAM block inputs and outputs is enabled, but the number of pins and wiring required increases significantly

Engineering Contradiction:

Improveaccess to RAM inputs and outputsVSAvoidnumber of pins and wiring

Core Design Contradiction:

Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent extracts the testing function from the functional pins by introducing dedicated scan-in and scan-out pins that are separate from the normal address and data pins. This allows testing access without requiring the functional pins to be repurposed or additional pins to be added for each signal, thereby reducing overall complexity while enabling comprehensive RAM testing.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces scan chains as an intermediary mechanism between the test equipment and the RAM block. The scan chains act as a mediator that transfers test patterns through a series of flip-flops to eventually reach the RAM inputs and capture outputs, enabling indirect but comprehensive testing without direct pin access to all RAM signals.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If functional test is used to exercise all RAM addresses, then testing can be performed without additional pins, but significant chip-level activity is required which cannot effectively observe and control RAM inputs and outputs

Engineering Contradiction:

Improvepin usageVSAvoidobservation and control of RAM inputs and outputs

Core Design Contradiction:

Device complexityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent extracts the observation and control functions from the functional operation by introducing dedicated scan-in and scan-out pins that are separate from the normal address and data pins. This allows testing access without requiring the functional pins to be repurposed or additional pins to be added for each signal, thereby reducing overall complexity while enabling comprehensive RAM testing.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces scan chains as an intermediary mechanism between the test equipment and the RAM block. The scan chains act as a mediator that transfers test patterns through a series of flip-flops to eventually reach the RAM inputs and capture outputs, enabling indirect but comprehensive testing without direct pin access to all RAM signals.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Extent of automation

If ATPG tools are used to detect faults, then automatic fault detection is enabled, but the tools cannot handle setting addresses or creating timing sequences to change RAM contents and check outputs

Engineering Contradiction:

Improveautomatic fault detectionVSAvoidability to control RAM inputs and observe outputs

Core Design Contradiction:

Extent of automationVSAdaptability or versatility

Solution Approach 1:

The patent makes the scan chain mechanism universal by designing it to perform multiple functions: it can load test patterns, control RAM inputs, capture outputs, and facilitate ATPG operations. This multi-functional design allows ATPG tools to effectively control RAM contents and observe outputs while maintaining automatic fault detection capabilities.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces scan chains as an intermediary mechanism between the test equipment and the RAM block. The scan chains act as a mediator that transfers test patterns through a series of flip-flops to eventually reach the RAM inputs and capture outputs, enabling indirect but comprehensive testing without direct pin access to all RAM signals.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7287203B1Testing embedded RAM blocks by employing RAM scan techniques

Publication Date: 2007.10.23 ADVANCED MICRO DEVICES INC

AI summary

A method is provided for testing RAM blocks embedded in an integrated circuit. The method provides a scan circuit embedded in an integrated circuit. The scan circuit includes a RAM block, a plurality of first flip-flops each sending a read address to the RAM block, a plurality of second flip-flops each sending a write address to the RAM block, a plurality of third flip-flops each sending an enable signal to the RAM block, a plurality of fourth flip-flops, and a multiplexer receiving an output from the RAM block, the first, second, third and fourth flip-flops being connected in series. An internal scan test is performed by loading serial data into the first, second, third and fourth flip-flops.