Embedded RDL Package Structure for Smaller Via Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges in forming efficient redistribution layers (RDLs) for integrated fan-out packages, particularly in ensuring accurate alignment and minimizing the size of vias to increase trace spacing, which affects the integration density and packaging efficiency.
Innovation Solution
The method involves forming a trench and a via hole in the dielectric layer, followed by a seed layer and conductive layer deposition, with the conductive layer and seed layer being removed to create an embedded RDL structure that is level with the dielectric layer's surface, avoiding misalignment and undercut issues, and allowing for increased trace spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If via size is reduced to increase trace spacing, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the via hole before forming the trace, and by pre-defining the via position using the trench structure as a reference. This sequence ensures that the via is positioned accurately before the trace is deposited, reducing alignment precision requirements while enabling smaller via sizes for increased trace spacing and integration density.
Solution Approach 2:
The patent introduces a trench structure as an intermediary element that serves as a reference for via positioning. The trench acts as a physical guide that mediates the alignment between the via and the subsequent trace, reducing the need for high manufacturing precision in via placement while allowing for compact via dimensions.
2Reliability
If embedded RDL structure is formed to prevent misalignment, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the via structure with the trace structure by forming the via hole through the dielectric layer and then depositing the conductive trace that directly connects to the via. This integration of via and trace formation into a single embedded RDL structure eliminates misalignment issues between separate via and trace components, improving reliability while the modular approach keeps device complexity manageable.
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.