Embedded RDL Package Structure Without Via Pad Misalignment
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming redistribution layer (RDL) structures within integrated fan-out packages, particularly in achieving precise alignment and minimizing undercut issues during the formation of via pads.
Innovation Solution
The method involves forming a trench and a via hole in the dielectric layer, followed by the deposition of a seed layer and a conductive layer to create an embedded RDL structure. This approach eliminates the need for via pads, thereby avoiding misalignment and undercut issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via pads are used in RDL structure formation, then electrical connection is achieved, but misalignment and undercut issues occur
Solution Approach 1:
The patent removes the via pad component from the RDL structure entirely. Instead of forming separate via pads that require precise alignment, the invention directly forms conductive plugs within via holes that extend through the dielectric layer, eliminating the via pad layer and its associated alignment challenges.
Solution Approach 2:
The conductive path is segmented into distinct components: conductive plugs formed in via holes, trace patterns formed in the dielectric layer, and connection pads. This segmentation allows each component to be formed independently with optimized process parameters, reducing overall structure complexity.
2Length of moving object
If RDLs are embedded in dielectric layer, then spacing for traces is increased, but manufacturing process complexity increases
Solution Approach 1:
The via holes are formed preliminarily in the dielectric layer before the trace patterns are created. This preliminary action allows the conductive plugs to be pre-positioned, providing reference points for subsequent trace formation and ensuring adequate spacing without requiring complex real-time alignment processes.
Solution Approach 2:
The patent utilizes the vertical dimension by forming conductive plugs that extend through the dielectric layer thickness, rather than relying solely on planar via pad structures. This dimensional approach increases trace spacing in the horizontal plane while maintaining electrical connectivity through the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the effective embedding of RDLs within the dielectric layer, reducing the size of the via and increasing the spacing for traces, which enhances the packaging efficiency and reliability of integrated fan-out packages.
Implementation Method 1
the deposition of a seed layer and a conductive layer to create an embedded RDL structure
Implementation Method 2
the deposition of a seed layer and a conductive layer
Data Source
AI summary
A package structure is provided. The package structure includes a die, an encapsulant and a RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.