Embedded Reference Cells in Non-Volatile Memory Arrays
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Solution Overview
Problem
Existing non-volatile memory devices have separate reference cells that do not track process details or array environments of data cells, leading to integration challenges and performance issues.
Innovation Solution
Embedding reference memory cells within the array of non-volatile memory cells, with each row containing multiple reference cells evenly spaced, sharing the same type and structure as data cells, and using a high voltage decoder and low voltage row decoder for connection to bit lines, sense amplifiers, and decoders for improved integration and tracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If reference cells are embedded within the memory array, then process variation tracking and sensing accuracy are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges reference cells with data cells by embedding them within the same memory array structure. Reference cells are positioned at specific locations (e.g., every Nth column) within the array, allowing them to share the same physical environment, process variations, and readout circuitry as data cells. This integration enables reference cells to track process variations and array environment effects, improving sensing accuracy while avoiding the complexity of separate reference arrays.
Solution Approach 2:
The patent applies local quality by positioning reference cells at specific locations within the memory array rather than uniformly distributing them or placing them in a separate array. Reference cells are strategically positioned (e.g., every Nth column) to represent local process variations and environmental effects in specific regions of the array, enabling targeted compensation without requiring comprehensive coverage throughout the entire array.
2Device complexity
If reference cells are placed outside the memory array, then device complexity is reduced, but process variation tracking capability deteriorates
Solution Approach 1:
The patent merges reference cells with data cells by embedding them within the same memory array structure. Reference cells are positioned at specific locations (e.g., every Nth column) within the array, allowing them to share the same physical environment, process variations, and readout circuitry as data cells. This integration enables reference cells to track process variations and array environment effects, improving sensing accuracy while avoiding the complexity of separate reference arrays.
3Measurement precision
If multiple reference cells are evenly spaced in each row, then spatial effect averaging is improved, but area overhead increases
Solution Approach 1:
The patent applies local quality by positioning reference cells at specific locations within the memory array rather than uniformly distributing them or placing them in a separate array. Reference cells are strategically positioned (e.g., every Nth column) to represent local process variations and environmental effects in specific regions of the array, enabling targeted compensation without requiring comprehensive coverage throughout the entire array.
Solution Approach 2:
The patent implements partial action by placing reference cells at specific intervals (every Nth column) rather than at every position. This selective placement provides sufficient spatial effect averaging for compensation while minimizing the area overhead. The parameter N is optimized to achieve the desired balance between averaging capability and area utilization.
Data Source
AI summary
An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.