Embedded-Reference Comparator Circuit for Low-Power ADC Quantization

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Solution Overview

Problem

Analog-to-digital converters (ADCs) require numerous comparators, leading to high power consumption and circuit costs, as well as kickback errors and parasitic capacitances that degrade ADC performance.

Innovation Solution

A multiple-reference-embedded comparator (MREC) circuit that includes a tail current source, an input transistor pair for first pre-amplification, and multiple embedded reference branches for second pre-amplification and discrete-time comparison, sharing the tail current source and input differential pair.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple dynamic comparators are used to achieve high-speed ADC quantization, then the ADC speed and quantization performance are improved, but the power consumption and circuit area increase substantially

Engineering Contradiction:

ImproveADC quantization speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

Multiple embedded reference branches share a common tail current source and input differential pair, merging previously separate comparator resources to reduce overall power consumption while maintaining multiple comparison functions

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared tail current source and input differential pair serve multiple embedded reference branches simultaneously, making these components multi-functional and reducing the total number of components needed

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple dynamic comparators with resistor ladders are used, then the comparison function is enhanced, but the power consumption and heat generation increase

Engineering Contradiction:

Improvecomparison accuracyVSAvoidheat generation

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

Multiple embedded reference branches share a common tail current source, merging previously separate current sources to reduce total power consumption and heat generation while maintaining comparison accuracy

Inventive Principle:

Principle #5Merging (Combining)

3Ease of operation

If traditional dynamic comparators are used, then the comparison function is provided, but kickback errors and parasitic capacitances degrade ADC performance

Engineering Contradiction:

Improvecomparison functionVSAvoidkickback errors and parasitic capacitances

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The comparison function is segmented into multiple embedded reference branches with different reference voltages, allowing kickback errors to be distributed and canceled across multiple comparisons rather than affecting a single comparison

Inventive Principle:

Principle #1Segmentation

4Adaptability or versatility

If multiple separate comparators are used, then the comparison capability is increased, but the circuit area and cost increase

Engineering Contradiction:

Improvecomparison capabilityVSAvoidcircuit area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple embedded reference branches are merged to share common components (tail current source, input differential pair), reducing the total circuit area while maintaining the capability to perform multiple comparisons with different reference voltages

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12308843B2Multiple-reference-embedded comparator and comparison method thereof

Publication Date: 2025.05.20 NAT CHENG KUNG UNIV

AI summary

A multiple-reference-embedded comparator (MREC) circuit includes a tail current source circuit; an input transistor pair, coupled to the tail current source circuit, configured to receive differential input voltages and perform a first pre-amplification to generate first differential amplified voltages according to the differential input voltages; and a plurality of embedded reference (ER) branches, each coupled to the input transistor pair, each configured to perform a second pre-amplification to generate second differential amplified voltages according to the first differential amplified voltages, and to perform a discrete-time comparison to generate differential output voltages according to the second differential amplified voltages.