Embedded Semiconductor Region Layout for CMOS Latch-Up Suppression

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Solution Overview

Problem

CMOS devices are vulnerable to latch-up, a short circuit condition that can lead to high current flow and potential destruction due to the formation of parasitic bipolar junction transistors, triggered by factors like voltage spikes and radiation, which disrupts proper circuit operation.

Innovation Solution

An embedded semiconductor region (ESR) structure is formed in the vicinity of the deep N-well of NMOSFET or PMOSFET devices to reduce current along parasitic latch-up paths, increasing the holding voltage and suppressing high-temperature induced degradation, compatible with existing CMOS fabrication processes without requiring additional masks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If deep N-well structures are formed to eliminate noise in CMOS, then noise isolation is improved, but latch-up susceptibility increases due to formation of parasitic bipolar junction transistors

Engineering Contradiction:

Improvenoise isolationVSAvoidlatch-up susceptibility

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

An embedded semiconductor region (ESR) with opposite polarity doping is introduced as an intermediary structure between the deep N-well and the P-type substrate. This ESR acts as a mediator that disrupts the formation of parasitic bipolar junction transistors while preserving the noise isolation function of the deep N-well structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The doping concentration and polarity are locally modified by introducing the ESR with opposite polarity doping in specific regions. This local quality change prevents latch-up in critical areas while maintaining the overall deep N-well noise isolation structure.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If standard CMOS fabrication processes are used, then manufacturing simplicity is maintained, but latch-up protection is insufficient without additional structural modifications

Engineering Contradiction:

Improvefabrication process simplicityVSAvoidlatch-up protection

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The ESR formation process is merged with existing CMOS fabrication steps, particularly utilizing the same ion implantation or diffusion processes already employed for well formation. This integration provides latch-up protection without requiring separate additional manufacturing steps.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The ESR structure serves multiple functions: it prevents latch-up by disrupting parasitic BJT formation, and it can be formed using the same doping processes already used for deep N-well and P-well formation, making the solution universally applicable to standard CMOS processes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240243129A1Embedded semiconductor region for a latch-up susceptibility improvement

Publication Date: 2024.07.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.