Embedded Semiconductor Region Layout for CMOS Latch-Up Suppression

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Solution Overview

Problem

CMOS devices are vulnerable to latch-up, a condition where a low-impedance path forms between the power supply and ground, causing short circuits and potential destruction due to overcurrent, triggered by factors like voltage spikes and radiation.

Innovation Solution

An embedded semiconductor region (ESR) structure is formed in the vicinity of the deep N-well of NMOSFET or PMOSFET devices to reduce current along parasitic latch-up paths, increasing the holding voltage and suppressing high-temperature induced degradation, compatible with existing CMOS fabrication processes without requiring additional masks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If deep N-well structures are formed to eliminate noise, then noise isolation is improved, but latch-up susceptibility increases

Engineering Contradiction:

Improvenoise isolationVSAvoidlatch-up susceptibility

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

An embedded semiconductor region (ESR) with opposite polarity is introduced as an intermediary element between the deep N-well and the P-type substrate. This ESR acts as a mediator that disrupts the parasitic bipolar transistor formation path, thereby reducing latch-up susceptibility while preserving the noise isolation function of the deep N-well structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The embedded semiconductor region is selectively placed at specific locations within the deep N-well structure, creating local variations in doping concentration and polarity. This local modification targets the critical areas where parasitic bipolar transistors are most likely to form, reducing latch-up susceptibility without compromising the overall noise isolation performance.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If conventional CMOS structures are used, then manufacturing simplicity is maintained, but latch-up protection is insufficient

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidlatch-up protection

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The embedded semiconductor region is integrated into the existing deep N-well fabrication process by combining the ESR formation step with the deep N-well doping process. This merging of functions allows the latch-up protection feature to be added without requiring separate manufacturing steps or additional masks, thereby maintaining manufacturing simplicity while improving latch-up protection.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11973080B2Embedded semiconductor region for latch-up susceptibility improvement

Publication Date: 2024.04.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.