Embedded Resistor Formation via High-K Metal Gate Deposition
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Solution Overview
Problem
Existing methods for generating embedded resistors in semiconductor integrated circuits are inefficient and cause oxide damage, requiring additional photolithography steps and being unsuitable for high-K metal gate devices due to low and non-linear resistance characteristics.
Innovation Solution
A method involving shallow trench isolation, deposition of silicon and metal gate materials like Hafnium Oxide and Titanium Nitride, and reduced photolithography steps to form polyconductor resistors with fewer additional steps, allowing for the creation of embedded resistors with adjustable resistance and reduced oxide damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional implant methods are used to form embedded resistors, then manufacturing cost is reduced, but oxide damage occurs and additional photolithography steps are required
Solution Approach 1:
The patent changes the formation method from implant-based to deposition-based, altering the physical-chemical parameters of the process. This eliminates oxide damage while maintaining cost-effectiveness by using standard deposition equipment already present in high-K metal gate fabrication lines.
Solution Approach 2:
The patent copies the transistor gate formation process to create resistors. By using the same deposition sequences and materials (high-K metal gate stack) for both transistors and resistors, the process eliminates additional photolithography steps while achieving the desired resistor structures.
2Adaptability or versatility
If traditional methods are used, then existing process parameters are utilized, but the resistance characteristics are low and non-linear
Solution Approach 1:
The patent uses composite material structures (high-K metal gate stack with multiple layers) to achieve superior resistance characteristics. The combination of different materials (oxide layer, metal layer, silicide layer) enables both high linearity and adaptability to existing process parameters.
Solution Approach 2:
The patent modifies material composition and layer thickness parameters within the deposition process to achieve linear resistance characteristics. By controlling the high-K metal gate stack formation parameters, the patent achieves precise resistance values with improved linearity while reusing existing process windows.
3Ease of manufacture
If additional photolithography steps are added for resistor formation, then resistor structures can be formed, but manufacturing complexity increases
Solution Approach 1:
The patent merges the resistor formation process with the transistor gate formation process. Both structures are formed simultaneously using the same high-K metal gate deposition sequence, eliminating the need for separate photolithography steps and reducing manufacturing complexity.
Solution Approach 2:
The patent creates a universal process that forms both transistors and resistors using the same equipment and material deposition sequences. The high-K metal gate stack formation serves dual purposes, enabling resistor structures without additional photolithography while maintaining transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively generates embedded resistors with adjustable resistance and reduced oxide damage, suitable for high-K metal gate devices, and allows for dynamic reprogramming of logic chips using eFUSEs, enhancing performance tuning and reducing manufacturing complexity.
Implementation Method 1
oxidizing the PC
Implementation Method 2
depositing at least one of an oxide material or a metal gate material on the oxidized surface
Data Source
AI summary
Generating an embedded resistor in a semiconductor device includes forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed above the STI region; etching the silicon layer to yield a polyconductor above the STI region; oxidizing the polyconductor; depositing an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer above the STI region; patterning a transistor gate with a photo-resist mask on another portion of the silicon layer away from the STI region; and etching the silicon layer to yield a transistor structure away from the STI region and a resistor structure above the STI region.