Embedded Resistor Resistivity Tuning via Surface Treatment
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Solution Overview
Problem
Existing methods for embedding thin film resistors in interconnect dielectric materials in semiconductor devices are complex, expensive, and suffer from topography issues, variation in sheet resistivity, and tuning precision challenges.
Innovation Solution
A semiconductor structure with a resistor embedded in interconnect dielectric material is developed, where a doped metallic insulator layer is converted into an electrical conducting resistive material through a controlled surface treatment process, allowing for patterned resistor structures with tunable resistivity using metallic nitrides, oxides, or nitride-oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior art methods are used to embed thin film resistors in interconnect dielectric material, then resistors can be formed, but the process becomes complicated and expensive
Solution Approach 1:
The patent changes the physical and chemical parameters of the metallic insulator layer through controlled surface treatment (oxidation, nitridation, or carbidation) to transform it from an insulating state to a resistive state. By adjusting treatment conditions such as oxygen partial pressure, temperature, and treatment duration, precise control over the resulting resistor's resistivity is achieved, simplifying the overall process while maintaining reliability
Solution Approach 2:
The patent introduces a metallic insulator layer as an intermediary material that serves dual purposes: initially as an insulator during processing, then as the precursor for forming the resistive material. This intermediary layer enables a streamlined process where the same layer serves multiple functions, reducing the need for separate resistor formation steps and decreasing process complexity
2Reliability
If prior art methods are used to embed thin film resistors in interconnect dielectric material, then resistors can be formed, but cost increases
Solution Approach 1:
The metallic insulator layer is designed to perform multiple functions: serving as the resistor body, providing adhesion to underlying layers, and enabling controlled resistivity through surface treatment. This multi-functionality eliminates the need for separate material layers and processing steps, thereby reducing manufacturing cost while maintaining reliable resistor formation
Solution Approach 2:
The metallic insulator layer self-transforms into the resistive material through controlled surface treatment, eliminating the need for separate resistor formation processes. The layer essentially services its own transformation from insulator to resistor, reducing the need for additional processing equipment and materials, thereby lowering manufacturing costs
3Reliability
If thin film resistors are embedded in interconnect dielectric material, then resistors are formed, but topography issues arise that degrade chip yield
Solution Approach 1:
The patent applies local quality changes by treating only the surface portion of the metallic insulator layer to create the resistive material, while the bulk layer remains as the original metallic insulator. This localized transformation allows for precise control over resistor properties and minimizes topography variations, thereby improving chip yield while maintaining reliable resistor formation
4Reliability
If prior art methods are used to form thin film metal resistors, then resistors can be formed, but sheet resistivity variation occurs
Solution Approach 1:
The controlled surface treatment process incorporates feedback mechanisms where treatment parameters (oxygen partial pressure, temperature, duration) are adjusted based on desired resistivity targets. This feedback control enables precise tuning of the resistor's sheet resistivity, minimizing variation and improving manufacturing precision while maintaining reliable resistor formation
5Reliability
If prior art methods are used to embed thin film metal resistors, then resistors can be formed, but tuning precision is insufficient
Solution Approach 1:
The patent employs multiple可调 parameters in the surface treatment process (oxygen partial pressure, temperature, treatment duration, and treatment depth) to achieve precise tuning of resistor resistivity. By independently controlling these parameters, fine adjustments to the resistor's electrical properties can be made, significantly improving tuning precision while maintaining reliable resistor formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a semiconductor structure with design flexibility and controlled resistivity, reducing complexity and cost while improving yield and precision in resistor formation.
Implementation Method 1
The controlled surface treatment process converts the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer
Implementation Method 2
The electrical conducting resistive material is selected from the group consisting of a metallic nitride, a metallic oxide, and a metallic nitride-oxide
Data Source
AI summary
The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.