Embedded Resistor Layout for High-Voltage Transient Suppression
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Solution Overview
Problem
Existing semiconductor devices with resistor elements in a chip face challenges in effectively managing high voltage applications, leading to potential breakdowns due to rapid voltage changes.
Innovation Solution
The semiconductor device incorporates a resistor circuit with high and low resistance parts, along with dummy resistors and buried electrodes, to mitigate rapid voltage changes and enhance voltage tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistor element is directly connected to a high voltage input electrode, then the resistor can function as a voltage divider, but rapid voltage changes cause breakdown due to potential difference with adjacent resistor layers
Solution Approach 1:
A dummy wiring is introduced as an intermediary element between the high voltage input electrode and the first resistor layer. This dummy wiring forms a parasitic capacitor with the first buried electrode, which acts as a buffer to suppress rapid voltage changes (dV/dt) before they reach the resistor layers, preventing breakdown while maintaining voltage division functionality
Solution Approach 2:
The parasitic capacitor formed by the dummy wiring and first buried electrode provides beforehand cushioning by absorbing rapid voltage changes before they can cause breakdown in the resistor layers. This protective mechanism is built into the structure in advance, cushioning the resistor elements from harmful voltage transients
2Reliability
If multiple resistor layers are arranged adjacently to form a voltage divider, then voltage detection capability is improved, but potential difference between adjacent layers increases susceptibility to breakdown
Solution Approach 1:
The dummy wiring serves as a mediator that electrically connects adjacent resistor layers through parasitic capacitance rather than direct connection. This intermediary capacitive coupling allows voltage detection across multiple layers while preventing direct potential difference stress that would cause breakdown
Solution Approach 2:
The invention changes the electrical connection parameter between adjacent resistor layers from direct conductive connection to capacitive coupling through dummy wiring. This parameter change transforms the interaction mode, allowing voltage detection while reducing susceptibility to breakdown from rapid voltage changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses rapid voltage changes, improving the withstand voltage of the resistor chip and reducing the risk of breakdowns.
Implementation Method 1
a first dummy wiring capacitively coupled to a first buried electrode
Data Source
AI summary
A semiconductor device includes an insulating layer formed on a semiconductor substrate; and a resistor embedded in the insulating layer; wherein the resistor comprises: a first resistor layer; a first buried electrode electrically connected to one end of the first resistor layer; a first dummy wiring capacitively coupled to the first buried electrode; a second resistor layer disposed adjacent to the first resistor layer; and a second buried electrode electrically connected to one end of the second resistor layer and electrically connected to the first dummy wiring.