Embedded Resistors in ReRAM Cells for Thermal Stability
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Solution Overview
Problem
Transistor-based flash memory faces limitations in endurance, power consumption, and scalability, making it inadequate for meeting the increasing demands of nonvolatile memory in modern electronic devices.
Innovation Solution
The development of resistive random access memory (ReRAM) cells with a resistive portion and a resistive switching portion, integrated as part of the same layer, using conductive silicon oxide and silicon oxide materials with specific atomic ratios, and formed through continuous deposition processes like chemical vapor deposition or physical vapor deposition, to create a simpler manufacturing process with high thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor-based flash memory is used to meet increasing storage demand and speed requirements, then storage capacity and access speed can be improved, but endurance, power consumption, and scalability are worsened
Solution Approach 1:
The patent changes the fundamental operating parameter from transistor-based quantum tunneling to resistive switching based on oxygen vacancy migration. This parameter change enables the memory to achieve both high speed and high endurance by utilizing a different physical mechanism that does not suffer from the wear limitations of transistor-based flash memory
Solution Approach 2:
The patent replaces the mechanical/electrical system of transistor gating and quantum tunneling with a purely electronic resistive switching system based on ionic migration of oxygen vacancies. This substitution eliminates the mechanical wear and electrical breakdown issues inherent in transistor-based flash memory, thereby improving endurance while maintaining fast access speeds
2Quantity of substance
If transistor-based flash memory is used to increase storage capacity, then storage density can be improved, but power consumption and scalability are worsened
Solution Approach 1:
The patent changes the storage mechanism parameter from charge trapping in floating gate transistors to resistive state changes via oxygen vacancy migration. This enables lower power consumption because the resistive switching requires significantly less energy than the high-voltage quantum tunneling process needed in flash memory, while still achieving high storage density through scalable nanoscale device dimensions
3Manufacturing precision
If conventional separate layer fabrication is used for resistive portion and resistive switching layer, then manufacturing precision can be improved, but device complexity and fabrication steps are worsened
Solution Approach 1:
The patent merges the resistive portion and resistive switching layer into a single continuously deposited layer. This is achieved by adjusting deposition parameters (such as oxygen partial pressure or precursor ratios) during a single atomic layer deposition process to create regions with different oxygen stoichiometry within the same physical layer, thereby reducing fabrication complexity while maintaining manufacturing precision through in-situ parameter control
Solution Approach 2:
The patent applies local quality by creating regions with different oxygen concentrations within the same deposited layer. By varying deposition conditions locally during the continuous deposition process, the patent generates distinct functional regions (resistive portion with higher oxygen content and resistive switching portion with lower oxygen content) without requiring separate physical layers, thus simplifying the overall device structure while maintaining precise control over each region's properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
ReRAM cells exhibit improved thermal stability, reduced current spiking, and enhanced endurance, enabling efficient data storage with lower power consumption and simplified manufacturing, addressing the limitations of traditional flash memory.
Implementation Method 1
forming the second layer includes exposing the substrate to one or more precursors that may include silicon and chromium
Implementation Method 2
forming the second layer includes sputtering a chromium containing target and a silicon containing target
Implementation Method 3
forming the second layer includes sputtering a chromium containing target and a silicon containing target, and reducing a ratio of power applied to the chromium containing target to power applied to the silicon containing target
Data Source
AI summary
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The methods may include forming a first layer on a substrate, where the first layer is operable as a bottom electrode. The methods may also include forming a second layer, where the second layer includes a resistive portion and a resistive switching portion. The resistive portion may be configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The resistive portion may have a substantially constant resistance. The resistive portion may include, at least in part, a conductive silicon oxide. The resistive switching portion may be configured to switch between a first resistive state and a second resistive state. The resistive switching portion may include, at least in part, silicon oxide. The methods may also include forming a third layer, where the third layer is operable as a top electrode.