Embedded RRAM Structure for Protecting Source/Drain Contacts
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Solution Overview
Problem
The integration of resistive random-access memory (RRAM) structures with transistor structures in integrated circuits (ICs) often results in structural damage to the source/drain (S/D) structures and introduces thickness variations in the RRAM resistive material, leading to low device reliability and performance degradation.
Innovation Solution
A semiconductor device structure with an embedded RRAM structure is fabricated by sandwiching a layer of resistive material between one of the S/D contacts and a metal electrode, ensuring the S/D structures remain undamaged and allowing for controlled thickness of the RRAM layer through blanket deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If RRAM structures are integrated with transistor structures in the back end of the line, then memory functionality is added to the IC, but the S/D structures suffer structural damage and reliability decreases
Solution Approach 1:
The patent separates the RRAM structure formation into distinct stages: first forming the transistor structures, then later forming the RRAM structures in the back end of the line. This segmentation allows the S/D structures to be fully formed and stabilized before RRAM processing begins, preventing structural damage while still achieving memory functionality integration.
Solution Approach 2:
The patent performs preliminary actions by completing all transistor structure formation, including source/drain regions and contacts, before initiating RRAM structure formation. This preliminary completion of critical structures protects them from damage during subsequent RRAM processing steps.
2Productivity
If line and via pitch in interconnect layers are scaled down with each technology generation, then device density increases, but the space between RRAM structures is reduced and manufacturing complexity increases
Solution Approach 1:
The patent addresses pitch scaling challenges by utilizing vertical dimensionality in the back end of the line for RRAM structure formation. Instead of horizontally packing RRAM structures closer together in already-scaled interconnect layers, the solution employs vertical stacking and depth utilization, allowing high density without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of the embedded RRAM structure, thereby improving the overall performance and reliability of the IC by isolating the RRAM structure from the S/D structures and allowing precise control over the RRAM thickness.
Implementation Method 1
allowing for controlled thickness of the RRAM layer through blanket deposition
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.