Embedded RRAM Structure for S/D Contact Reliability
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Solution Overview
Problem
The integration of resistive random-access memory (RRAM) structures with transistor structures in integrated circuits (ICs) often results in structural damage to the source/drain (S/D) structures and introduces thickness variations in the RRAM resistive material, leading to low device reliability and performance degradation.
Innovation Solution
A semiconductor device structure with an embedded RRAM structure is fabricated by sandwiching a layer of resistive material between one of the S/D contacts and a metal electrode, thereby isolating the RRAM structure from the S/D structures and allowing for controlled thickness of the resistive material using a blanket deposition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If RRAM structures are integrated with transistor structures in the back end of the line, then memory functionality is added to the IC, but structural damage to the source/drain structures occurs and device reliability decreases
Solution Approach 1:
The patent divides the RRAM structure into separate components: the resistive material layer is deposited as a distinct layer between the S/D contact and the metal electrode, rather than being integrated into the S/D structure itself. This segmentation prevents damage to the S/D structures while maintaining memory functionality.
Solution Approach 2:
The resistive material is extracted from the S/D structure and placed as a separate layer above the S/D contact. This extraction eliminates the structural damage caused by integrating RRAM directly into the S/D regions, while still enabling memory operation through the separated RRAM structure.
2Quantity of substance
If RRAM structures are formed between interconnect layers with scaled-down pitch, then device density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the RRAM resistive material deposition with the existing blanket deposition processes used for other interconnect layers. By forming the resistive material layer using the same blanket deposition approach as for copper or metal alloy layers, the manufacturing process complexity is reduced despite the scaled-down pitch and increased device density.
3Area of stationary object
If RRAM structures are formed with scaled-down space between structures, then area utilization improves, but thickness control of resistive material becomes difficult
Solution Approach 1:
The patent uses a universal blanket deposition process that serves multiple functions: it deposits the resistive material for RRAM structures and simultaneously forms the interconnect metal layers. This multi-functional approach maintains consistent thickness control across all layers, including the resistive material, even as the space between structures is scaled down to improve area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and yield of the embedded RRAM structure, enhancing the overall performance and reliability of the IC by preventing structural damage to the S/D structures and ensuring well-controlled resistive material thickness.
Implementation Method 1
allowing for controlled thickness of the resistive material using a blanket deposition process
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.