Embedded SAR-ADC Reuse in ACiM for Low-Overhead ReLU
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Solution Overview
Problem
The existing analog compute-in-memory (ACiM) architectures face significant power consumption and latency issues due to inefficient analog to digital converter (ADC) and digital to analog converter (DAC) operations, particularly in neural networks, where frequent data conversion between analog and digital domains reduces the benefits of analog computing.
Innovation Solution
An embedded successive approximation register (SAR)-ADC is integrated with in-memory capacitor ladders that sample and store charge during MAC operations, allowing for reuse during digitization, reducing the need for additional area and power-consuming DACs and buffers, and implementing a least significant bit (LSB) skipping scheme for activation functions like ReLU to minimize data conversion overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequent data conversion between analog and digital domains is performed in ACiM architecture, then neural network operations can be executed, but power consumption increases and latency increases
Solution Approach 1:
The patent merges the ADC and DAC functions into a single shared capacitor ladder structure. The same capacitors used for analog MAC operations are reused for digital conversion, eliminating separate ADC and DAC hardware blocks. This merging reduces the overall component count, decreases area usage, and lowers power consumption while enabling both analog computation and digital conversion functions.
Solution Approach 2:
The capacitor ladder is designed to serve multiple functions: it performs analog MAC operations during computation phases and serves as the conversion element for both ADC and DAC operations during digitization phases. This multi-functionality eliminates the need for dedicated ADC/DAC hardware, reducing power consumption and area while maintaining full operational capability.
2Measurement precision
If full-fledged ADCs are implemented in ACiM architecture, then accurate digitization is achieved, but area usage increases and power consumption increases
Solution Approach 1:
The patent combines the ADC functionality with the existing capacitor ladder infrastructure. Instead of implementing a separate full-fledged ADC with its own capacitor array, the design reuses the MAC operation capacitors for conversion purposes. This merging achieves accurate digitization while dramatically reducing the area required, as no additional capacitor banks are needed.
Solution Approach 2:
The capacitor ladder serves itself dual purposes: it performs analog computation during MAC phases and performs digital conversion during ADC phases. The same physical capacitors provide both computational weight storage and conversion reference functions, eliminating the need for separate ADC hardware and reducing overall area usage while maintaining digitization accuracy.
3Reliability
If separate DACs and buffers are added to ACiM architecture, then data conversion is improved, but power consumption increases and area usage increases
Solution Approach 1:
The patent merges DAC functionality into the same capacitor ladder structure used for MAC operations. The capacitors that store analog weights during computation are reused as the DAC reference capacitors during conversion. This eliminates the need for separate DAC hardware and associated buffers, reducing power consumption and area while maintaining data conversion quality through the same high-precision capacitor array.
4Productivity
If LSB skipping scheme is implemented for ReLU activation, then data conversion overhead is reduced, but computational precision may be affected
Solution Approach 1:
The patent implements LSB skipping where only the most significant bits are converted and processed, while the least significant bits are skipped or coarsely quantized. For ReLU activation functions, this partial conversion approach maintains sufficient precision for the non-linear operation while dramatically reducing the number of conversion steps required, thereby increasing throughput with acceptable precision trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption and area usage by eliminating the need for full-fledged ADCs, improving efficiency, throughput, and scalability, while maintaining accuracy and reducing calibration needs.
Implementation Method 1
analog to digital converter (ADC) and digital to analog converter (DAC) operations in ACiM architecture
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.