Embedded SCR ESD Protection Structure for LDMOS Reliability

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Solution Overview

Problem

Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) events, and existing on-chip protection circuits, including LDMOS devices, are also susceptible to ESD-induced damage.

Innovation Solution

A structure for an electrostatic discharge protection device is provided, comprising a semiconductor substrate with a well, a field-effect transistor, and a silicon-controlled rectifier, all with doped regions, to effectively manage and dissipate ESD currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an LDMOS device is used as a protection device in an on-chip protection circuit, then the integrated circuit is protected from ESD events, but the protection device itself is susceptible to damage from ESD events

Engineering Contradiction:
Improveprotection circuit reliabilityVSAvoidESD damage to protection device
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent embeds a silicon-controlled rectifier (SCR) structure within the well region of the LDMOS device. The SCR is formed by creating additional doped regions (first and second doped regions of second conductivity type, and first and second doped regions of first conductivity type) within the drift well and extension region of the LDMOS device. This nested configuration allows the SCR to provide self-protection to the LDMOS device during ESD events, enabling the protection circuit to handle higher ESD currents without damaging the protection device itself.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the protection device is designed to handle high ESD currents, then the integrated circuit is better protected, but the device complexity increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidprotection device structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the LDMOS device and SCR structure into a single integrated protection device. The SCR is formed using the existing well region of the LDMOS device, sharing common structural elements such as the drift well, extension region, and contact structures. This merging approach allows the protection circuit to benefit from both the high-voltage handling capability of the LDMOS device and the self-protection capability of the SCR, while minimizing the increase in device complexity through shared structural components.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure effectively protects integrated circuits from ESD events by integrating a laterally-diffused metal-oxide-semiconductor device and an embedded silicon-controlled rectifier, ensuring the protection device remains functional even at higher gate bias values.

Implementation Method 1

An integrated circuit may be exposed to random electrostatic discharge (ESD) events that can direct large and damaging ESD currents to the sensitive devices of the integrated circuit

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

the protection circuit triggers a protection device to enter a low-impedance state that conducts the ESD current to ground and thereby shunts the ESD current away from the sensitive devices

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250031457A1Self-protected electrostatic discharge protection devices
Publication Date: 2025.01.23 GLOBALFOUNDRIES US INC
  • US20250031457A1 patent drawing
  • US20250031457A1 patent drawing
  • US20250031457A1 patent drawing

AI summary

Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.