Embedded Security Circuit via Directed Self-Assembly

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Solution Overview

Problem

Current integrated circuit security techniques are costly and complex, requiring additional process steps for implementing physically unclonable functions (PUFs), which increases the complexity and cost of fabricating secure chips.

Innovation Solution

The integration of embedded security circuits using directed self-assembly (DSA) techniques, where block copolymers and homopolymers are used to create fin field effect transistor (finFET) devices with unbroken and broken fin channels, forming a unique security code within the integrated circuit, leveraging the same photolithography mask for both regular and security regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional process steps are added to implement physically unclonable functions (PUFs) for chip security, then security reliability is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvechip securityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines security circuit fabrication with the existing photolithography process by using the same mask for both regular and security regions. The block copolymer self-assembly is integrated into the standard fabrication flow, merging security implementation with conventional manufacturing steps rather than adding separate processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The block copolymer system performs self-assembly directed by the photolithography pattern, automatically creating the security code structure without requiring additional lithography steps or manual intervention. The material self-organizes into the desired pattern based on the guiding pattern pitch, reducing process complexity.

Inventive Principle:
Principle #25Self-service

2Reliability

If additional process steps are added to implement physically unclonable functions (PUFs) for chip security, then security reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvechip securityVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines security circuit fabrication with the existing photolithography process by using the same mask for both regular and security regions. The block copolymer self-assembly is integrated into the standard fabrication flow, merging security implementation with conventional manufacturing steps rather than adding separate processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent uses block copolymer materials that can be deposited and processed in a cost-effective manner. The guiding patterns are formed using standard photolithography materials, and the self-assembly process uses inexpensive chemical treatments to remove one block and leave the other, creating a low-cost security implementation.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If different pitches are used in security and non-security segments for creating broken fins, then security code uniqueness is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesecurity code uniquenessVSAvoidpitch control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the pitch parameter of the guiding patterns in the security region relative to the non-security region. This pitch difference causes the block copolymer self-assembly to produce broken fins in the security region while maintaining intact fins elsewhere, creating the security code through a controllable parameter variation.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different guiding pattern pitches locally in different regions of the chip. The security region has a distinct pitch from the non-security region, creating local structural differences that generate the security code without affecting the overall device functionality.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the cost-effective fabrication of integrated circuits with a random and unique security code, difficult to attack, by incorporating security features into the existing semiconductor fabrication process, reducing additional process complexity and costs.

Implementation Method 1

depositing a self-assembling material comprising at least one of (i) a block copolymer and (ii) a block copolymer/homopolymer combination on the plurality of directed self-assembly guiding patterns, wherein the self-assembling material comprises a third distinct pitch, and annealing the self-assembling material to initiate a self-assembly process directed by the plurality of directed self-assembly guiding patterns

Methodology Applied
Scientific EffectSelf-assembly: Self-Assembly

Implementation Method 2

annealing the self-assembling material to initiate a self-assembly process directed by the plurality of directed self-assembly guiding patterns

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS10141339B2Embedded security circuit formed by directed self-assembly
Publication Date: 2018.11.27 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10141339B2 patent drawing
  • US10141339B2 patent drawing
  • US10141339B2 patent drawing

AI summary

Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.