Embedded Semiconductor Packaging via Adhesive-Assisted Alignment
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Solution Overview
Problem
Conventional semiconductor packaging methods face issues with positional deviations and alignment errors due to heat lamination and laser processing, leading to potential electrical connection failures and high costs.
Innovation Solution
A packaging substrate with an embedded semiconductor component is fabricated using an assisting layer with apertures filled with a filling material, where bumps on the semiconductor chip align with the apertures, and an adhesive member encapsulates the chip, allowing for precise positioning and electroplating to form conductive vias without heat lamination or laser processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If heat lamination is used to form the dielectric layer, then the dielectric layer can be formed to fill the cavity, but the semiconductor chip may have positional deviation due to pressure during heat lamination, resulting in alignment deviation between conductive vias and electrode pads
Solution Approach 1:
The semiconductor chip is fixed to the carrier board before the dielectric layer is formed. This preliminary fixing action prevents positional deviation during subsequent heat lamination and pressing operations, ensuring that the chip remains in the correct position for accurate via alignment with electrode pads
Solution Approach 2:
A recess is formed in the carrier board at the chip position, and the chip is embedded in this recess. This structural cushioning prevents the chip from moving under pressure during heat lamination, as the recess physically constrains the chip position while allowing the dielectric layer to be formed around it
2Ease of manufacture
If laser processing is used to form vias in the dielectric layer, then vias can be formed, but the process requires high cost, has low speed and is easy to damage the semiconductor chip
Solution Approach 1:
The patent replaces laser processing with mechanical drilling or punching methods to form vias in the dielectric layer. These mechanical methods are faster, less costly, and do not risk damaging the semiconductor chip through excessive heat, while still achieving the required via formation for electrical connections
Solution Approach 2:
The patent changes the processing parameters from high-energy laser treatment to lower-energy mechanical removal methods. This parameter change reduces processing cost and time while eliminating the risk of chip damage associated with laser processing, maintaining via formation effectiveness through alternative physical mechanisms
3Manufacturing precision
If the semiconductor chip is fixed to the carrier board before forming the dielectric layer, then positional deviation is prevented, but the chip may be damaged by external forces during the process
Solution Approach 1:
A recess is formed in the carrier board at the chip position, and the chip is embedded in this recess. The recess acts as a protective cushion that absorbs external forces and prevents direct impact on the chip, while still allowing accurate positioning and secure fixation before dielectric layer formation
Solution Approach 2:
The semiconductor chip is nested within the recess of the carrier board, creating a protective structure where the recess surrounds and protects the chip. This nested configuration provides mechanical protection against external forces while maintaining precise positioning for subsequent processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances alignment precision, prevents positional deviations, and eliminates the drawbacks of conventional laser processing, such as low precision and high costs, while ensuring reliable electrical connections.
Implementation Method 1
an adhesive member disposed in the first dielectric layer and located right on the active surface of the semiconductor chip and the electrode pads
Implementation Method 2
the first wiring layer has a plurality of first conductive vias disposed in the adhesive member and electrically connecting to the electrode pads
Data Source
AI summary
A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively.