Embedded Semiconductor Cell Trench Design
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Solution Overview
Problem
The reduction in size of semiconductor devices poses challenges in maintaining electrical properties, particularly due to damage to gate structures during manufacturing, which affects the performance of logic and memory cells.
Innovation Solution
A semiconductor device design with embedded cells, where a floating gate is formed within a trench of a silicon substrate, separated by dielectric layers, and a control gate is embedded, preventing damage during the manufacturing process of different regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate heights of logic cells and memory cells are made different to optimize their respective functions, then the electrical performance of each cell type can be improved, but the manufacturing process causes damage to the gates of memory cells due to the height difference
Solution Approach 1:
The patent embeds the memory cell gates vertically within the substrate using trenches, transitioning from a planar gate structure to a three-dimensional embedded structure. This dimensional change allows the memory cell gates to be positioned at different depths, protecting them from damage during subsequent manufacturing processes while maintaining their required heights for optimal electrical performance.
Solution Approach 2:
The memory cell gates are nested within trenches in the substrate, with dielectric layers surrounding them. This nesting structure protects the gates from external damage during manufacturing while allowing them to maintain their functional height. The control gates are embedded within the substrate matrix, surrounded by protective dielectric material.
2Volume of moving object
If the feature size is reduced to decrease device size, then the density and cost per integrated circuit unit are improved, but the electrical properties deteriorate due to incomplete element profiles and gate damage
Solution Approach 1:
By embedding gates vertically in trenches rather than keeping them planar, the patent maintains complete gate profiles even as feature sizes are reduced. The vertical embedding allows gates to retain their full height and structural integrity, ensuring complete profiles and optimal electrical properties despite smaller device dimensions.
Solution Approach 2:
The gates are formed and embedded in trenches before subsequent manufacturing steps are performed. This preliminary embedding action protects the gates from damage that would occur during later processing steps, ensuring complete profiles and good electrical properties are maintained throughout the manufacturing process.
Data Source
AI summary
A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.